In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter. The register is configured to cause the digital-analog converter to generate N pairs of differential voltages (N1), to cause the digital-analog converter to generate an (N+1).sup.th pair of differential voltages by causing one of a positive side and a negative side of the digital-analog converter to output an (N+1).sup.th differential voltage and causing the other of the positive side and the negative side to output a differential voltage equal to the N.sup.th differential voltage as an (N+1).sup.th differential voltage, and to output a digital signal corresponding to a comparison signal having a smallest voltage among (N+1) comparison signals.

High speed of an analog-digital converter of a semiconductor device is achieved. A voltage quantizer circuit includes: a first comparator including a first input transistor inputting differential input voltages, and defining a value of a first bit of a digital signal; and a second comparator including a second input transistor being different from the first input transistor, and defining a value of a second bit of the digital signal. A correction code decision circuit decides a correction code for correcting a common-mode voltage of the differential input voltages, based on a conversion end signal output from the voltage quantizer circuit. A common-mode voltage regulator circuit regulates the common-mode voltage by adding or subtracting a corrected voltage based on the correction code to or from the differential input voltages.

A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit.

Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2.sup.n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2.sup.n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.

Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions.

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.

The differential amplifier circuit includes: first conductivity type first to N.sup.th differential stages each causing a current corresponding to the first or second voltage received at the non-inverting input terminal to flow to a first node and a current corresponding to the output voltage signal received at the inverting input terminal to a second node; a second conductivity type differential stage receiving one of the first and second voltages at the non-inverting input terminal and receiving the output voltage signal at the inverting input terminal, and being activated when the digital data value is within a predetermined range to cause a current corresponding to the one voltage to flow to a third node and a current corresponding to the output voltage signal to a fourth node; and an output amplification stage generating the output voltage signal based on the currents respectively flowing to the first to fourth nodes.

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.

A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.