The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.

The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result. By using the pre-comparison and charge redistribution technologies, the number of comparators of different stages of pipelined sub ADC is reduced and the low power consumption design is achieved, signal sample-and-hold and residual signal amplification establishing are simultaneously carried out, thus improving the conversion rate.

A multiplying digital-to-analog converter (MDAC) includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switch circuit. During a sampling cycle, the switch circuit connects a pre-defined voltage and reference voltages to the pre-sampling capacitor circuit, disconnects the pre-sampling capacitor circuit from an input port of the operational amplifier and the sampling capacitor circuit, disconnects an output port of the operational amplifier from the sampling capacitor circuit, and connects a voltage input to the sampling capacitor circuit. During a conversion cycle, the switch circuit connects the pre-sampling capacitor circuit to the sampling capacitor circuit, disconnects the pre-defined voltage and the reference voltages from the pre-sampling capacitor circuit, connects the pre-sampling capacitor circuit to the input port of the operational amplifier, connects the output port of the operational amplifier to the sampling capacitor circuit, and disconnects the voltage input from the sampling capacitor circuit.

An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.

A photoelectric conversion device includes a plurality of pixels configured to output analog voltage signals in response to incident light; an analog memory configured to store the analog voltage signals output from the plurality of pixels; and an analog/digital (A/D) converter configured to perform A/D conversion on the analog voltage signal from the analog memory. The plurality of pixels includes N pixels configured to simultaneously output analog voltage signals to the analog memory. The A/D converter includes (N1) or less A/D converters configured to perform A/D conversion on the analog voltage signals that have been simultaneously output from the N pixels and stored in the analog memory.

A gain calibration device for an ADC residue amplifier includes a DAC and a flash ADC. The DAC is configured to convert the digital signal to an analog signal, and the DAC includes a calibration module used in the gain calibration of the ADC residual amplifier. The flash ADC is configured to generate a digital signal, the flash ADC includes a plurality of comparators, the total number of the plurality of comparators is equal to the number of output bits of the flash ADC, and the comparators are configured to be unevenly distributed in an input range.

An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.

An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.

A high-speed and high-precision photonic analog-to-digital conversion device capable of realizing intelligent signal processing. Learning ability of deep learning technology is utilized to learn the nonlinear response and channel mismatch effect of the system and configure optimal parameters of the deep network. Deterioration of photonic analog-to-digital conversion system performance caused by nonlinear distortion and channel mismatch distortion is eliminated in real time, and performance indicators thereof are improved. By using the induction and deduction ability of deep learning technology, intelligent signal processing of the input signal is realized, and users are provided with digital signals that meet the requirements. It's important for improving the performance of microwave photonic systems that require high sampling rate, high time precision, and high sampling accuracy, such as microwave photonic radar and optical communication systems, and also critical to improve the signal processing ability of such systems under complex conditions.