A multiplying digital to analog converter includes first and second inputs for receiving first and second differential input signals. A differential amplifier has first and second differential input nodes and first and second differential output nodes. A first capacitor is coupled in series with a first switch between the first differential input node and the first input. The first capacitor is further coupled to at least one reference voltage supply node via one or more further switches. A second capacitor is coupled between the first differential input node and the first differential output node. A third capacitor is coupled between the first differential input node and the first input.

A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously averages out the bandwidth mismatch contribution to the offset.

A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.

A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously averages out the bandwidth mismatch contribution to the offset.

In a pipelined Successive Approximation Register Analog to Digital Converter, SAR ADC, a Process, Temperature, and Voltage (PVT)-dependent bias voltage is generated and used to bias the inputs of comparators in at least the first SAR stage and residual amplifier (RA). This achieves a stable biasing and an operating point of the comparators and RA input stages that is independent of PVT variations, by tracking PVT variations in such a way that variations in MOS threshold voltage and drain-source voltage are counteracted. Additionally, a threshold common mode voltage is generated from the PVT-dependent voltage, which controls the amplification duration of the RAs such that the final RA output common mode voltage is substantially equal to the PVT-dependent voltage, which is used to bias the inputs of successive SAR stages. The threshold is set to account for logic delays in terminating the amplification based on the threshold comparison, to achieve the desired common mode amplifier output. The dependency on PVT of the threshold additionally cancels temperature variation from a differential stage transconductance of the RA. Further temperature stabilization is achieved by boosting the charge output by the RA to a capacitive load during part of the amplification.