An analog-to-digital converter is connected to a crossbar array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and processing circuitry. The voltage generator includes at least one resistive memory element including a same resistive material as the resistive element included in the crossbar array, and is configured to generate a first voltage based on a reference voltage and the at least one resistive memory element and to divide the first voltage to generate at least one divided voltage. The processing circuitry is configured to compare a signal voltage generated from the crossbar array with the at least one divided voltage to generate at least one comparison signal and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

An embodiment electronic circuit includes an electronic switch comprising a load path, and a control circuit configured to drive the electronic switch. The control circuit is configured to operate in one of a first operation mode and a second operation mode based at least on a level of a load current of the electronic switch. In the first operation mode the control circuit is configured to generate a first protection signal based on a current-time-characteristic of the load current and drive the electronic switch based on the first protection signal. The control circuit is configured to generate a status signal such that the status signal has a wakeup pulse when the operation mode changes from the second operation mode to the first operation mode and, after the wakeup pulse, a signal level representing a level of the load current.

An analog to digital converting module includes a comparator, at least one digital to analog convertor, and a reference buffer. The comparator is configured to compare a first input signal and a second input signal so as to output a comparing signal. The at least one at least one digital to analog convertor includes at least one capacitor. The reference buffer is configured to provide a reference signal. The at least one digital to analog convertor receives the reference signal such that a ripple signal is generated according to a change of a voltage of the reference signal. The capacitance of the capacitor of the at least one digital to analog convertor is adjusted based on the ripple signal.

A voltage regulator circuit included in a computer system may include multiple phase circuits each coupled to a regulated power supply node via a corresponding inductor. The phase circuits may modify a voltage level of the regulated power supply node using respective control signals generated by a digital control circuit that processes multiple data bits. An analog-to-digital converter circuit may compare the voltage level of the regulated power supply node to multiple reference voltage levels and sample the resultant comparisons to generate the multiple data bits.

The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3 increase in the number of iterations required to complete the SAT attack.

A modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.

An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator, and a successive approximation register (SAR) control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an output of the comparator and to an input of the CDAC. The SAR control circuit includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.