The present disclosure provides a voltage divider circuit utilizing non-volatile memory devices. The non-volatile memory device may include, for example, a memristor device, an MRAM (Magnetoresistive random access memory) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, etc. The voltage divider circuit may include one or more first non-volatile memory devices that form a resistor ladder. The resistor ladder may produce a plurality of reference voltages when the resistor ladder is connected between two voltages.

A signal conditioning circuit and a measurement device are provided. A selection circuit of the signal conditioning circuit outputs a first conduction signal when a voltage value of an input voltage signal is less than a threshold value of a voltage threshold signal, such that a first segmented voltage conditioning sub-circuit conditions, based on the received first conduction signal, the input voltage signal and outputs a first output voltage signal. The selection circuit outputs a second conduction signal when the voltage value of the input voltage signal is greater than the threshold value of the voltage threshold signal, such that the second segmented voltage conditioning sub-circuit conditions the input voltage signal and outputs a second output voltage signal.

A voltage regulator circuit included in a computer system may include multiple phase circuits coupled to a regulated power supply line via corresponding one of multiple inductors. The phase circuits may modify a voltage level of the regulated power supply line using respective control signals generated by a digital control circuit that processes multiple data bits. An analog-to-digital converter circuit may compare the voltage level of the regulated power supply node to multiple reference voltage levels and sample the resultant comparisons to generate the multiple data bits.

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

Multiple-bit parallel successive approximation (SA) Flash analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SA Flash ADC circuit includes a digital-to-analog converter (DAC) circuit that receives reference voltage and trial bit codes, and generates DAC analog signals. The SA Flash ADC circuit includes parallel comparator stages, each including one or more comparator circuits equal to two (2) raised to a number of digital bits of the corresponding parallel comparator stage, quantity minus one (1). Each comparator circuit receives an analog input signal and corresponding DAC analog signal, and generates a digital signal. The digital signal of each comparator circuit is logic high if the analog input signal has a greater voltage than the corresponding DAC analog signal, and logic low if the analog input signal has a smaller voltage. The digital signals corresponding to each parallel comparator stage are used to generate a digital output signal.

An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.

Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the bandpass signal with a bandpass filter, generating the real and imaginary parts of the complex analytic signal with a quadrature hybrid, determining the amplitude of the complex analytic signal by adding an even power-law transform of the real and imaginary parts of the complex analytic signal, and determining the phase of the complex analytic signal by comparing the real and imaginary parts of the complex analytic signal to zero and comparing an even power-law transform of the real and imaginary parts of the complex analytic signal to each other. Analog to digital converters and methods of converting complex analytic signals to digital signals are also disclosed.

A pixel of a pixel array is provided. The pixel includes a low frequency path configured to receive an input signal from a corresponding photodetector. The low frequency path includes a passive imaging circuit provided along the low frequency path, the passive imaging circuit configured to output an analog imaging signal and a flash analog to digital converter (ADC) that receives the analog imaging signal and processes the analog imaging signal to output a coarse digitized signal.