A successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator, a threshold generator and a controller. The comparator receives an analog signal and the SAR ADC outputs an output codeword. The comparator performs a plurality of first comparisons and a plurality of second comparisons. The controller determines a plurality of most significant bits of the output codeword according to a plurality of first comparison results corresponding to the first comparisons. The first comparisons are performed by comparing the analog signal with a plurality of first thresholds. The controller determines a plurality of least significant bits of the output codeword according to a plurality of second comparison results corresponding to the second comparisons. The second comparisons are performed by comparing the analog signal with a second threshold. The controller controls the threshold generator to produce the plurality of first thresholds and the second threshold according to the first comparison results.

A computing-in-memory circuit comprises a computing element array and an analog-to-digital conversion circuit. The computing element array is utilized for analog computation operations. The computing element array includes memory cells, a first group of computing elements, and a second group of computing elements. The first group of computing elements provides capacitance for analog computation in response to an input vector and receives data from the plurality of memory cells and the input vector. The second group of computing elements provides capacitance for quantization. Each computing element of the computing element array is based on a switched-capacitors circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the first and second groups of computing elements are selectively coupled to the signal terminal and the reference terminal.

An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.

An analog-to-digital converting device configured to convert an analog signal into a digital signal, including a meta-stability detection unit configured to output a meta-stability signal based on a comparison result, wherein the comparison result is determined by comparing a comparison voltage of each bit of the digital signal with the analog signal; a counter configured to count a number of times that the comparison voltage of each bit of the digital signal is compared with the analog signal; and a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number.

An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.

A successive approximation register analog to digital converter includes a sampling circuitry, a comparator circuit, and a controller circuitry. The sampling circuitry generates first and second signals according to a sampled signal. The comparator circuit compares the first signal with the second signal to generate first decision signals. The controller circuitry generates digital codes according to the first decision signals, and controls the comparator circuit to perform comparisons repeatedly to generate second decision signals, in order to generate a digital output according to the digital codes, a statistical noise value, and the second decision signals. The controller circuitry further controls the sampling circuitry and the comparator circuit to perform comparisons repeatedly according to the sampled signal having an initial level during an initial phase, in order to generate third decision signals, and performs a statistical calculation to obtain the statistical noise value according to the third decision signals.

An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.

In certain aspects, an analog-to-digital converter (ADC) includes a comparator having a first input, a second input, and an output. The ADC also includes a digital-to-analog converter (DAC) coupled to the first input of the comparator, a switching circuit, a first capacitor coupled between the first input of the comparator and the switching circuit, a second capacitor coupled between the first input of the comparator and the switching circuit, and an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to the switching circuit. The ADC further includes a first switch coupled between the output of the amplifying circuit and the DAC, and a successive approximation register (SAR) having an input and an output, wherein the input of the SAR is coupled to the output of the comparator, and the output of the SAR is coupled to the DAC.

In accordance with some embodiments of the present disclosure, an apparatus including a crossbar circuit is provided. The crossbar circuit may include a plurality of cross-point devices with programmable conductance, a transimpedance amplifier (TIA), and an analog-to-digital converter (ADC). The TIA is configured to produce an output voltage based on an input current corresponding to a summation of current from a first plurality of the cross-point devices. The ADC is configured to generate a digital output corresponding to a digital representation of the output voltage of the TIA. To generate the digital output, the ADC is to generate, using a comparator, a first plurality of bits (e.g., MSBs) of the digital output by performing a coarse conversion process and a second plurality of bits (e.g., LSBs) of the digital output by performing a fine conversion process on a sample-and-hold voltage produced in the coarse conversion process.