A sigma-delta analog-to-digital converter includes: a subtractor for subtracting a feedback signal from an analog input signal; a loop filter for processing the output signal from the subtractor to generate a filtered signal; a signal comparing circuit for selectively operating in an offset detection mode or a signal comparison mode, wherein the signal comparing circuit generates an error signal irrelevant to the relative magnitude between the filtered signal and a reference signal in the offset detection mode, and generates a comparison signal corresponding to the relative magnitude between the filtered signal and the reference signal in the signal comparison mode; an offset calibration control circuit for calibrating the offset of the signal comparing circuit and for controlling the signal comparing circuit to alternately switch between the offset detection mode and the signal comparison mode; and a digital-to-analog converter for generating the feedback signal according to the comparison signal.

Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.

A motion sensor with sigma-delta analog-to-digital converter (ADC) having improved bias instability is presented herein. Differential outputs of a differential amplifier of the sigma-delta ADC are electrically coupled, via respective capacitances, to differential inputs of the differential amplifier. To minimize bias instability corresponding to flicker noise that has been injected into the differential inputs, the differential inputs are electrically coupled, via respective pairs of electronic switches, to feedback resistances based on a pair of switch control signals. In this regard, a first feedback resistance of the feedback resistances is electrically coupled to a first defined voltage, and a second feedback resistance of the feedback resistances is electrically coupled to a second defined reference voltage. The differential outputs are electrically coupled to differential inputs of a differential comparator of the sigma-delta ADC, and complementary outputs of the differential comparator comprise the pair of switch control signals.

A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.

A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.

An offset compensation circuit comprises an error signal generation block arranged for receiving an input phase and an output phase, and for generating an error signal indicative of an error between the input phase and the output phase. Means are provided for combining the error signal with an offset compensation signal, yielding an offset compensated signal. A loop filter is arranged for receiving the offset compensated signal and for outputting the output phase. An offset compensation block is arranged for receiving the output phase and for determining the offset compensation signal. The offset compensation signal comprises at least a contribution proportional to a periodic function of the output phase.

A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.

A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.

Chopping techniques that suppress fold-back into the signal band and spreads the offset across the spectrum are described. By using various techniques, chopping may be performed with a variable frequency clock to spread the offset across the signal spectrum. Spreading the offset across the signal spectrum means that there are no longer large spurious tones at a few frequencies.