Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Voltage data capture circuits and techniques. In one example, a circuit includes a differential transconductance stage, a differential transimpedance stage, and an analog to digital converter (ADC). The differential transconductance stage is configured to convert a differential input voltage into a differential current, and the differential transimpedance stage is configured to convert the differential current into a differential output voltage. The ADC is configured to sample the differential output voltage to produce a digital output signal. The circuit may further include a common-mode voltage regulator configured to regulate a common-mode input voltage for the differential transimpedance stage. The circuit can be used, for instance, in a battery monitoring system, or other voltage monitoring application.

A switched capacitor circuit includes main, common-mode feedback, and control circuits. The main circuit includes a sampling capacitor and an operational amplifier. The sampling capacitor samples an input signal with first and second control signals. The common-mode feedback circuit includes: a first capacitor connected between an output of the operational amplifier and a node; a second capacitor connected in parallel to the first capacitor via a first switch group; a third capacitor connected in parallel to the first capacitor via a second switch group; and a third switch group and a fourth switch group. The control circuit turns on the first switch group and the fourth switch group in synchronization with a first common control signa based on the first control signal, and turns on the second switch group and the third switch group in synchronization with a second common control signa based on the second control signal.

A sensor readout circuitry comprises: a delta-sigma modulator; an input stage for receiving an analog sensor input signal, wherein a transconductance amplifier and a current mirror incorporate a flipped voltage follower, wherein a feedback signal from a digital-to-analog converter of the delta-sigma modulator is received such that subtraction between the analog sensor input signal and the feedback signal is performed in the transconductance amplifier and mirrored by the current mirror to an output of the input stage; wherein the transconductance amplifier comprises a first, second and third chopper, whereby a chopping loop between the first, second and third choppers is formed including an input transistor and current sources and whereby the analog sensor input signal is in baseband at a node in which the feedback signal is received.

An analog-to-digital converter includes an input-signal chopping switch, an integrator, an output chopping switch, a quantizer, and a feedback switch. The integrator is located after the input-signal chopping switch. The integrator includes an operational amplifier, an integral capacitor, and an integral-capacitor-chopping input switch being at on an input side of the integral capacitor. The output chopping switch is on an output side of the operational amplifier. The quantizer is located after the output chopping switch. The feedback chopping switch is in a feedback path from an output of the quantizer to an input of the first integrator. The input-signal chopping switch, the integral-capacitor-chopping input switch, the output chopping switch, and the feedback chopping switch execute chopping at an identical frequency. The output chopping switch sets a polarity of an input value of the quantizer to be identical before and after the chopping.

A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a sigma-delta modulator having a modulator input and a modulator output, first system-level chopping switches located at the modulator input, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the sigma-delta modulator, second system-level chopping switches located downstream of the sigma-delta modulator and the auxiliary path, and a signal combiner configured to combine a modulator output signal generated by the sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.

The disclosure relates to an integrator circuit (300) for a Sigma-Delta, , modulator, the integrator circuit (300) comprising an integrator module (310) comprising a differential amplifier (301), a sampling module (320) comprising sampling capacitors (CS1p, CS2p, CS1n, CS2n) and a reference module (330) comprising first and second pluralities of reference capacitors (331.sub.1-x, 332.sub.1-x) connected between respective first and second lines (308, 309) and first and second pluralities of reference switches (331.sub.1-x, 332.sub.1-x) for connecting each of the reference capacitors (331.sub.1-x, 332.sub.1-x) to either a first reference terminal (324) or a second reference terminal (325). In operation, the reference switches (331.sub.1-x, 332.sub.1-x) are switched according to a thermometrically coded quantizer signal.

An analog-to-digital converter and a thermopile array. The analog-to-digital converter comprises: a reference voltage generation circuit comprising a voltage generation unit; a chopping modulation unit used to perform chopping modulation on a voltage signal generated by the voltage generation unit, and to modulate low frequency noise of the voltage signal into high frequency noise; and a low-pass filter used to eliminate the high frequency noise to obtain a reference voltage. The invention employs a simple structure to obtain a low noise reference voltage at low costs.

An audio processing circuit includes a clock generation circuit, a first analog-to-digital converter (ADC), a second ADC, a first data alignment circuit, and a second data alignment circuit. The clock generation circuit is configured to generate a first sampling clock and a second sampling clock. The first ADC is configured to convert an input signal into a first digital code according to the first sampling clock. The second ADC is configured to convert the input signal into a second digital code according to the second sampling clock. The first data alignment circuit is configured to receive the first digital code and generate a third digital code. The second data alignment circuit is configured to receive the second digital code and generate a fourth digital code.

A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a sigma-delta modulator having a modulator input and a modulator output, first system-level chopping switches located at the modulator input, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the sigma-delta modulator, second system-level chopping switches located downstream of the sigma-delta modulator and the auxiliary path, and a signal combiner configured to combine a modulator output signal generated by the sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.