A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).

A delta-sigma modulator generates a bitstream signal from a differential input signal including a first input signal and a second input signal by repeating a first operation and a second operation alternately. The delta-sigma modulator includes a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor, an operational amplifier, a first feedback capacitor, a second feedback capacitor, and a quantizer.

According to an embodiment, a sample-hold circuit according to this embodiment is made up of a first device having a first withstand voltage and a second device having a second withstand voltage lower than the first withstand voltage. The sample-hold circuit includes a first switch element, a first capacitor, a second switch element, a third switch element, and a fourth switch element. The first switch element has the first withstand voltage. The first switch element operates upon receiving a first signal output from the device having the first withstand voltage. The second switch element has the first withstand voltage. The third switch element has the second withstand voltage. The fourth switch element has the second withstand voltage.

A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

An integrator circuit (10) for use in a sigma-delta modulator (1) comprises a differential operational amplifier (130) with a first input node (E130a) and a second input node (E130b). The first input node (E130a) of the differential operational amplifier (130) is connected to a first current path (101) and the second input node (E130b) of the differential operational amplifier (130) is connected to a second current path (102). A first controllable switch (111) is arranged between the second input node (E130b) of the differential operational amplifier (130) and the first current path (101). A second controllable switch (112) is arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102). A third controllable switch (113) is arranged between a reference potential (RP) and the first current path (101). A fourth controllable switch (114) is arranged between the reference potential (RP) and the second current path (102).

A signal acquisition or conditioning amplifier can be configured and controlled to use correlated doubling sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power operational transconductance amplifier (OTA) capable of being powered down between CDS samplings, and which can be operated in a manner that provides good performance characteristics while still providing low or efficient power consumption. The amplifier and other signal processing circuitry can allow power to be scaled down, when less signal measurement throughput is needed, and to be scaled up, when more signal measurement throughput is needed. Such flexibility can help make the present approach useful for a wide range of signal acquisition and measurement applications. Precharging via buffer amplifiers can provide improved signal acquisition circuitry effective input impedance.

According to an embodiment, a sample-hold circuit according to this embodiment is made up of a first device having a first withstand voltage and a second device having a second withstand voltage lower than the first withstand voltage. The sample-hold circuit includes a first switch element, a first capacitor, a second switch element, a third switch element, and a fourth switch element. The first switch element has the first withstand voltage. The first switch element operates upon receiving a first signal output from the device having the first withstand voltage. The second switch element has the first withstand voltage. The third switch element has the second withstand voltage. The fourth switch element has the second withstand voltage.

A Sigma-Delta analog to digital converter (ADC) is described. The Sigma-Delta ADC includes a series arrangement of a gain tracker, a first discrete-time integrator stage and a quantizer between an ADC input and an ADC output. The Sigma-Delta ADC includes a digital to analog converter (DAC) having a DAC input and a DAC output connected to the gain tracker. The Sigma-Delta analog to digital converter includes a controller having a control input connected to the quantizer output. The controller provides a digital input to the DAC input and provides a gain control signal to the gain tracker.

A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).

A Sigma-Delta analog to digital converter (ADC) is described. The Sigma-Delta ADC includes a series arrangement of a gain tracker, a first discrete-time integrator stage and a quantizer between an ADC input and an ADC output. The Sigma-Delta ADC includes a digital to analog converter (DAC) having a DAC input and a DAC output connected to the gain tracker. The Sigma-Delta analog to digital converter includes a controller having a control input connected to the quantizer output. The controller provides a digital input to the DAC input and provides a gain control signal to the gain tracker.