An analog-to-digital converter includes: a sample/hold circuit, which samples an analog signal, and outputs a first voltage; a digital-to-analog conversion circuit, which converts a digital signal to output a second voltage; an amplifier, which amplifies the first voltage and the second voltage; a noise shaping filter, which integrates a residual voltage corresponding to a difference between the amplified first voltage and the amplified second voltage, and generates a first integration voltage and a second integration voltage; a comparator, which compares a sum of the amplified first voltage, the first integration voltage, and the second integration voltage with the amplified second voltage; and a SAR logic, which outputs the digital signal according to a comparison result of the comparator, and controls the digital-to-analog conversion circuit.

A delta-sigma modulation type A/D converter includes: a capacitively coupled amplifier having a sampling capacitor, a feedback capacitor, and an amplifier; a correlated double sampling type first integrator as a first-stage integrator, which is connected to the capacitively coupled amplifier without a switch; a second integrator arranged after the first integrator; a quantizer arranged after the second integrator and quantizing an output of the second integrator; and an D/A converter that D/A-converts an output of the quantizer and feeds back to any one of the capacitively coupled amplifier, the first integrator, and the second integrator.

In accordance with embodiments of the present disclosure, a method of neutralizing voltage kickback associated with a reference buffer of a switched capacitor based data converter having a first switched capacitor coupled to an output node of the reference buffer wherein the first switched capacitor comprises at least one first capacitor and at least one first switch may be provided. The method may include coupling a passive network to the output node of the reference buffer in response to a presence of a condition for encountering the voltage kickback in order to create an approximately equal and opposite voltage kickforward by the passive network to at least partially neutralize the voltage kickback.

Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.

An analogue to digital converter for converting the analogue output of a dual conversion gain pixel of an image sensor. The dual conversion gain pixel is operable to sequentially output a reset pixel value and a signal pixel value sequentially with both a first gain and a second gain different to the first gain. An image sensor comprising the analogue to digital converter, a system comprising the image sensor and a method are also described herein.

Presented herein is a three-state buffer circuit having a voltage follower for directly driving a sampling capacitor at an output terminal of the three-state buffer circuit. The three-state buffer circuit further includes a switched capacitor circuit connected at an input of the voltage follower and configured to control the voltage follower to operate in one of a plurality of states. The states are: a tracking state, at which the voltage follower is configured to provide an output voltage at the output terminal at a level corresponding to an input voltage at an input terminal of the three-state buffer circuit; a hold state, at which the voltage follower is configured not to provide any output voltage at the output terminal; and a reset state at which the voltage follower is configured to provide an output voltage at the output terminal at a reset voltage.