An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a digital-to-analog (D/A) conversion circuit, a comparison circuit and a control circuit. The track-and-hold circuit is configured to output a first signal based on an input signal. The D/A conversion circuit is configured to generate a second signal based on an N-bit logical signal. The comparison circuit is configured to generate a comparison result based on the first signal and the second signal. The control circuit is configured to generate the N-bit logical signal according to N comparison results from the comparison circuit.

A switched capacitor circuit includes a first capacitor, a second capacitor, and a switching circuit. The first capacitor is configured to receive a first signal. The second capacitor is configured to receive a second signal. The switching circuit is configured to selectively couple the first capacitor and the second capacitor to an input terminal of a quantizer according to at least one clock signal. In a first configuration of the switching circuit, the first capacitor is configured to store the first signal, and the second capacitor is configured to store the second signal. In a second configuration of the switching circuit, the first capacitor and the second capacitor are stacked in series, in order to transmit a combination of the first signal and the second signal to the input terminal of the quantizer.

A circuit device includes a selector to which first to n-th voltages are input, an A/D converter circuit to which output voltages of the selector are input as input voltages, and first to n-th quantization error hold circuits that hold charges corresponding to quantization errors in A/D conversion of the first to n-th voltages. The A/D converter circuit performs A/D conversion of an input voltage by a successive approximation operation using a charge redistribution type D/A converter circuit and performs k-th A/D conversion on an i-th voltage by using a charge held in an i-th quantization error hold circuit in (k1)th A/D conversion of the i-th voltage to output A/D conversion result data DOUT in which the quantization error is noise-shaped.

A switched capacitor circuit includes a first capacitor, a second capacitor, and a switching circuit. The first capacitor is configured to receive a first signal. The second capacitor is configured to receive a second signal. The switching circuit is configured to selectively couple the first capacitor and the second capacitor to an input terminal of a quantizer according to at least one clock signal. In a first configuration of the switching circuit, the first capacitor is configured to store the first signal, and the second capacitor is configured to store the second signal. In a second configuration of the switching circuit, the first capacitor and the second capacitor are stacked in series, in order to transmit a combination of the first signal and the second signal to the input terminal of the quantizer.

An analog-to-digital converter (ADC) device includes capacitor arrays, successive approximation register (SAR) circuitries, and noise shaping circuitries. The capacitor arrays sample an input signal by turns, in order to provide a sampled input signal. The SAR circuitries perform an analog-to-digital conversion by turns according to a combination of the sampled input signal, a first residue signal, and a second residue signal, in order to generate digital outputs. The noise shaping circuitries receive a corresponding residue signal of the first residue signal the second residue signal in response to the analog-to-digital conversion, and to shape and transmit the corresponding residue signal to the SAR circuitries.

A circuit device includes an A/D converter circuit that performs A/D conversion by successive approximation using a charge redistribution type D/A converter circuit having capacitor array circuits on the positive electrode side and the negative electrode side, and quantization error hold circuits that hold charges corresponding to a quantization error in the A/D conversion. The quantization error hold circuits include quantization error hold circuits on the positive electrode side and the negative electrode side having one ends connected to sampling nodes of the capacitor array circuits on the positive electrode side and the negative electrode side. The quantization error hold circuits on the positive electrode side and the negative electrode side are placed on a second direction side orthogonal to a first direction in which the capacitor array circuits on the positive electrode side and the negative electrode side are placed.

Disclosed is a successive approximation register (SAR) quantizer and a continuous-time sigma-delta modulator (CTSDM) using the SAR quantizer. The SAR quantizer is capable of generating M highly-significant bits as a digital output signal, and generating L lowly-significant bit(s) for the execution of noise shaping operation. Therefore, the SAR quantizer and the CTSDM can reduce the demand for the circuit area of a digital-to-analog converter and lower the delay of a critical path, so as to improve the performance and cut the cost.

A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.

Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal. In the error-feedback configuration, the gain-control capacitor is decoupled from the input sampling capacitor and receives a residue voltage from the SAR-ADC, such that the level of the analog signal determined in the amplification configuration varies depending on the residue voltage received onto the gain-control capacitor in the error-feedback configuration.