An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

This disclosure relates to a current-to-digital converter suitable for wide-ranging current sensing applications. In particular, the current-to-digital converter comprises a delta-sigma analogue-to-digital converter which utilizes a successive-approximation-register to control a modulation of the sensed current so that the digital conversion of the modulated sensed current by the delta-sigma analogue-to-digital converter may be done with high precision.

A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.

Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

Disclosed herein are systems and methods that describe a noise-shaping (NS) SAR architecture that can be simple, effective, and low power. In an aspect, a method includes the operation of receiving a first analog input; determining a first digital output based on the first analog input; obtaining a first quantization error for the first digital output; integrating the first quantization error; receiving a second analog input; and determining a second digital output based on the summation of the second analog input and the first integrated quantization error to perform noise-shaping.

Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

In one aspect, an apparatus includes: a first feedback digital-to-analog converter (DAC) to receive a first feedback signal from a first successive approximation register (SAR) and output a first analog signal; a comparator to compare the first analog signal with a reference voltage; the first SAR to store a digital value based on the comparison and provide the first feedback signal to the first DAC; a second feedback DAC to receive a modulated quantized residual error based on the comparison and output a second analog signal; a second SAR to store a quantized residual error; and a delta-sigma modulator (DSM) to modulate the quantized residual error and provide the modulated quantized residual error to the second feedback DAC.

A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

This disclosure describes apparatuses, methods, and techniques that enable a computing device to support a dynamic range of audio quality, varying bandwidths, varying sampling rates, numerous effective number of bits (ENOBs) resolutions, conserve power during an overall usage of the computing device, and enhance a user experience. To do so, the computing device utilizes a reconfigurable analog-to-digital converter (ADC). The reconfigurable ADC includes a successive-approximation-register (SAR) ADC, a noise-canceling circuit, and a noise-shaping circuit. The reconfigurable ADC can selectively operate in different modes of operation, in part, by enabling or disabling the noise-canceling circuit and the noise-shaping circuit.

Integrating ADC based sensing systems that convert the output of a measurement sensor to a digital value avoid conversion errors caused by sensor temperature variation during the conversion cycle. The systems may either include a primary integrating ADC and a residue ADC, and adjust rate of operation of the ADCs independently according to a sensed temperature of the measurement sensor, or the systems may differentiate an output of the residue ADC, and apply a temperature correction in accordance with the sensed temperature of the sensor to an output of the differentiator, integrate the temperature-corrected output of the differentiator and then combine the result with the output of the primary integrating ADC.