An amplifier circuit comprising: a delta-PWM-modulator, a three-level-DAC, a loop-integrator, and a comparator. The delta-PWM-modulator receives a digital-input-signal; and processes the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal. The delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulation of the digital-input-signal. The three-level-DAC receives the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provides a three-level-analogue-signal. The loop-integrator comprises: a virtual-ground-node-terminal configured to receive: (i) the three-level-analogue-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop; and an integrator-output-terminal configured to provide a loop-integrator-output-signal. The comparator comprises a comparator-input-terminal configured to receive the loop-integrator-output-signal; a comparator-reference-terminal configured to receive a triangular-reference-signal that corresponds to the integral of the square-wave-carrier-signal; and a comparator-output-terminal configured to provide a drive-signal suitable for driving an output-stage of the amplifier circuit.

A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

Transition smoothing apparatus for reducing spurious input to a system under feedback control connected to a control loop. The apparatus includes a loop filter to integrate an error between an input signal applied to the loop filter and an output signal of the system under feedback control, an analog-to-digital converter to provide digitized integrated error values, a controller to generate output values supplied to the system under feedback control in response to the digitized integrated error values and in a start-up sequence to control a feedback digital-to-analog converter according to the digitized integrated error values to supply a first control signal to the loop filter and control the system under feedback control to generate a second control signal, and an alignment detector to detect phase alignment between the first control signal and the second control signal to control a smooth transition into closed loop operation of the control loop.

A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.

The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal; a feedforward filter unit configured such that a modulator to which an output signal of the subtraction unit is input and which includes integrators of a second order or higher is in cascade connection, and configured to operate with a sampling frequency FS; a product-sum computing unit configured to operate with a sampling frequency (FS/n) (n: an integer of two or more) to perform product-sum computing of an output signal of each integrator of the feedforward filter unit; and a pulse width modulation unit configured to operate with the sampling frequency (FS/n) to perform pulse width modulation of an output signal of the product-sum computing unit to output a pulse width modulation signal.

The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal; a feedforward filter unit configured such that a modulator to which an output signal of the subtraction unit is input and which includes integrators of a second order or higher is in cascade connection, and configured to operate with a sampling frequency FS; a product-sum computing unit configured to operate with a sampling frequency (FS/n) (n: an integer of two or more) to perform product-sum computing of an output signal of each integrator of the feedforward filter unit; and a pulse width modulation unit configured to operate with the sampling frequency (FS/n) to perform pulse width modulation of an output signal of the product-sum computing unit to output a pulse width modulation signal.

Proposed is a technology related to a compensation method for excess loop delay (ELD) using a time division switching (TDS) technique. A delta-sigma modulator (DSM) to which the compensation method for excess loop delay is applied includes a single op-amp resonator (SOR) loop filter. The loop filter includes an operational amplifier, a plurality of capacitors connected to each other in series between an input terminal and an output terminal of the operational amplifier, and a plurality of resistor units connected in common to one among nodes between the plurality of capacitors. For at least two of the plurality of resistor units, a resistance value of each of the at least two resistor units is changed according to a clock signal, and a coefficient of a third-order transfer function of the loop filter is changed according to the clock signal, thereby effectively compensating for excess loop delay of the delta-sigma modulator.

System and method for error amplification and processing. For example, the system includes: a signal processing unit configured to receive a reference signal and a feedback signal and generate a digital pulse signal, a frequency of the digital pulse signal being associated with a difference between the reference signal and the feedback signal; a counter configured to receive the digital pulse signal and generate a counter output signal based on at least information associated with the digital pulse signal; and a digital-to-analog converter configured to receive the counter output signal and generate an output signal based on at least information associated with the counter output signal.