For a radio frequency (RF) receiver system (1) for providing magnetic resonance (MR) information from an examination space of a MR imaging system, a solution for increasing the dynamic range of the radio frequency (RF) receiver system (1) for a better imaging performance shall be created. A sigma delta ADC of the RF receiver system operates in single-bit mode with an automatic gain control (AGC) circuit used to control the DAC feedback strength thereby extending the dynamic range of the receiver to match the MRI signal. The present invention also refers to a magnetic resonance (MR) imaging system, a method A method for extending the dynamic range of a radio frequency (RF) receiver system, a software package for a magnetic resonance (MR) imaging system, a software package for upgrading a magnetic resonance (MR) imaging system and a computer program product.

Disclosed are a continuous-time delta-sigma analog-to-digital converter and an operation method thereof. More particularly, a continuous-time delta-sigma analog-to-digital converter, including: a linear integrator configured to generate a first output signal corresponding to a preset input voltage based on an operation of a linear Gm circuit that receives the preset input voltage; and a quantizer configured to generate a second output signal corresponding to the first output signal based on an operation of a body-driven VCO that receives the first output signal and to generate a digital output code corresponding to the second output signal based on an operation of a Frequency to Digital Converter (FDC) that receives the second output signal is disclosed.

A delta-sigma modulation apparatus divides an input signal into a plurality of signal blocks, inputs the plurality of signal blocks to a plurality of delta-sigma modulation circuits, and performs combining processing for combining a plurality of output signals from the plurality of delta-sigma modulation circuits.

An amplifier circuit includes a resistor divider (R.sub.REF) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d.sub.1, d.sub.2), resistor nodes (q) defined between adjacent resistive elements, and an input current source (I.sub.REF) connected or connectable to the first main node (a). The resistor divider (R.sub.REF) comprises two arrays of addressable switch elements controllable by a feedback signal (s.sub.FB) to be open or closed. The amplifier circuit includes a differential pair of transistors (T.sub.1, T.sub.2), wherein source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second node (b), gate terminals of the transistors (T.sub.1, T.sub.2) are connected to input signals (v.sub.1, v.sub.2), drain terminals of the transistors (T.sub.1, T.sub.2) are connected to current sources (I.sub.1, I.sub.2), and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the readout nodes (d.sub.1, d.sub.2). The amplifier circuit functions as a difference amplifier, wherein the bulk terminals affect a threshold of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

A processing apparatus includes: a distribution unit that divides an input signal into input signal blocks, and distributes, in dividing order, the divided input signal blocks to delta-sigma modulation circuits; a parallel circuit unit including the delta-sigma modulation circuits that perform delta-sigma modulation on the input signal blocks and output output signal blocks; and a coupling unit that couples the output signal blocks outputted from the parallel circuit unit, thereby to generate an output signal such that a first output signal block reflects a result obtained from a first delta-sigma modulation circuit, which performs delta-sigma modulation on a first input signal block corresponding to the first output signal block, performing delta-sigma modulation on the first input signal block, and a state of a second delta-sigma modulation circuit that performs delta-sigma modulation on a second input signal block located immediately before or after the first input signal block.