An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.

A partitioned delta-sigma modulator for high-speed applications includes a plurality of modulation stages arranged in parallel to input and output terminals of the modulator and interconnected to one another in series. In some aspects, each of the plurality of modulation stages is configured to combine a first error signal from a prior modulation stage of the plurality of modulation stages with a first digital signal to produce an adder signal. In some aspects, the first error signal includes a delay from the prior modulation stage. Each of the plurality of modulation stages is also configured to convert the adder signal having a first bit width into a quantized signal having a second bit width smaller than the first bit width. Each of the modulation stages is also configured to provide a second error signal based on the quantized signal to a subsequent modulation stage of the plurality of modulation stages.

An apparatus for a signal processor for Wide-Band Applications is provided. The signal processor includes a plurality of parallel branches. Each parallel branch includes a frequency shifter, a sigma-delta-modulator, and a filter. The output signal of each branch is combined via a signal recombiner. The signal processor is suitable for wide-band applications due to centering the zeros of the sigma-delta-modulator's noise transfer function and filter's noise transfer function at the frequency of the frequency shifter in the same branch of the signal processor. Centering these zeros at the frequency of the frequency shifter shapes the quantization noise added by the sigma-delta-modulator away from the input signal frequency to make it easier to remove the quantization noise. This wideband performance is also achieved due to the design of the embodiment's filters. The embodiments of this invention use filters with symmetric transition bands and a pass-band that is wide enough for use in wireless applications.

A nested mixed-radix DDSM can guarantee zero systematic frequency error when used as a divider controller in a fractional-N frequency synthesizer is described. This disclosure presents a nested cascaded mixed-radix DDSM architecture which can also guarantee zero systematic frequency error. In addition, the disclosure allows one to use higher order auxiliary modulators and shaped dither signal to eliminate feedthrough spurs completely. By increasing the number of levels in the cascade, the moduli of the individual modulator stages can be reduced, thereby increasing the speed of the synthesizer.

An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

A nested mixed-radix DDSM can guarantee zero systematic frequency error when used as a divider controller in a fractional-N frequency synthesizer is described. This disclosure presents a nested cascaded mixed-radix DDSM architecture which can also guarantee zero systematic frequency error. In addition, the disclosure allows one to use higher order auxiliary modulators and shaped dither signal to eliminate feedthrough spurs completely. By increasing the number of levels in the cascade, the moduli of the individual modulator stages can be reduced, thereby increasing the speed of the synthesizer.

An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.

A digital/analog conversion apparatus to convert a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter to reduce the number of bits of an input signal, a second data converter to convert the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.