The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Energy function values are determined for bits of the codeword based on soft information for the bits of the codeword. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

Devices, systems and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight, processing the N columns based on a message passing algorithm, and determining, based on the processing, a candidate version of the transmitted codeword, wherein the processing for each of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, the read operation and the CNU operation on each of the at least B columns spanning two or more time-steps.

The present disclosure relates to a method and an apparatus for decoding data packets in communication network. The method comprises receiving one or more data packets related to each of one or more data types; and decoding the one or more data packets using a parity check matrix associated with the corresponding data type, wherein the parity check matrix comprises a plurality of layers, arranged according to a combination of layers which is determined using a reinforcement model.

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Syndrome information and energy function values are determined for bits of the codeword. A bit flipping criterion is selected using the syndrome information from a plurality of values. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies the bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

A method and system for LDPC decoding method. In the method and system, an LDPC codeword is decoded using a quasi-cyclic matrix. A first message for variable nodes in a circulant column of the quasi-cyclic matrix and a second message for check nodes belonging to the circulant column are computed. Parity and syndrome are computed using the computed first and second messages. A bit error rate is calculated for both a first mode with no error in a parity portion of a codeword and a second mode with errors in the parity portion of the codeword.

According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.

Devices, systems, and methods for dynamic control of a quasi-cyclic low-density parity-check (QC-LDPC) bit-flipping decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from an irregular QC-LDPC code, performing a plurality of decoding iterations on the received noisy codeword, each of the plurality of decoding iterations comprising processing of N circulant matrices, performing, before processing a current circulant matrix in a current M-th iteration of the plurality of decoding iterations, operations that include computing a number of bit flips that have occurred over the processing of N previous circulant matrices, the N previous circulant matrices spanning the current M-th iteration and an (M−1)-th iteration, wherein M and N are positive integers, and wherein M≥2, and updating, based on the number of bit flips, a bit-flipping threshold, and processing, based on the updated bit-flipping threshold, the current circulant matrix.