The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

A decoding method and device are provided. The method includes: decoding grouped original data in parallel by a first decoding unit to obtain grouped decoded data; decoding merged grouped decoded data by a second decoding unit to obtain decoded data; and if the sum of the lengths of the decoded data is an integer multiple of an upper limit of the decoding times of the second decoding unit, updating the first decoding unit and the second decoding unit, and if the sum of the lengths of the decoded data is not an integer multiple of the upper limit of the decoding times of the second decoding unit, updating the second decoding unit to obtain the decoded data again, until the sum of the lengths of the decoded data is equal to a decoding length, and merging the decoded data to serve as a decoding result of the original data.

Methods, systems, and devices for wireless communications are described. Efficient low-density parity-check (LDPC) scheduling of layered decoding may include receiving a message encoded as an LDPC code that includes a number of check nodes and a number of bit nodes, applying a first number of decoding iterations to decoding the message, applying a second number of decoding iterations to decoding the message after the first number of decoding iterations are applied, and decoding the message through completion of both the first number of decoding iterations and the second number of decoding iterations. In some cases, only a portion of the number of check nodes is decoded during each of the first number of decoding iterations and all of the number of check nodes are decoded during each of the second number of decoding iterations.

A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.

A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

A method of processing a received message includes: receiving a message through a receiving terminal to obtain the received message; for each bit in the received message, determining a bit state of the bit according to a bit value of the bit; selectively changing the bit state of each bit according to at least a weighting vector and a current value of a flipping threshold, wherein the bit state has a plurality of change ranges; selectively flipping the bit according to the bit state; and adjusting the current value of the flipping threshold according to a number of times the bit has been flipped within a period of time, whether when the number of times the bit has been flipped within the period of time exceeds an upper limit, the flipping threshold adjustment unit increases the current value of the flipping threshold.

The present disclosure provides a decoding device. The decoding device includes an iteration number computing unit and a recursive decoder. The iteration number computing unit receives multiple packet parameters corresponding to a packet and computes a codeword-number-per-symbol according to packet parameters, in which the packet includes multiple symbols. The iteration number computing unit computes an iteration number according to the codeword-number-per-symbol. The recursive decoder is coupled to the iteration number computing unit, and performs a decoding operation on a codeword within a data field of the packet according to the iteration number.