A sense amplifier latch (SAL) provides complimentary outputs in a reset phase to feed them directly to the Decision Feedback Equalizer (DFE) taps from SAL soft decision (d1x & d1xb) to improve the performance of DFE first tap 1-UI (one unit-interval) critical timing. The latch generates the complimentary resetting values on differential outputs in reset time. The latch enables in the required time i.e., once evaluation is done it shuts the current sinking path. The latch can extrapolate to rail-to-rail input common mode range of operation.

An electronic device, includes an intelligent reflecting surface and an electronic device controller. The intelligent reflecting surface is configured to reflect all or a part of a received signal. The electronic device controller is configured to control the intelligent reflecting surface to determine a first phase of the intelligent reflecting surface to increase a relay gain of first data of the received signal, determine a second phase related to second data, and control a phase of the intelligent reflecting surface based on a sum of the first phase and the second phase to reflect the first data and the second data to a receiving device by beamforming.

A receiver circuit is provided. The receiver circuit includes an antenna configured to receive a radio frequency (RF) signal; a filter configured to filter the RF signal received by the antenna; and a passive mixer circuit configured to adjust a center frequency of the filtered RF signal to a predetermined frequency. The passive mixer circuit includes: a transformer which includes a first coil and a second coil that is separate from the first coil; a first passive mixer which is directly connected to a first end of the second coil; and a second passive mixer which is directly connected to a second end of the second coil and is separate from the first passive mixer.

A receiver circuit is provided. The receiver circuit includes an antenna configured to receive a radio frequency (RF) signal; a filter configured to filter the RF signal received by the antenna; and a passive mixer circuit configured to adjust a center frequency of the filtered RF signal to a predetermined frequency. The passive mixer circuit includes: a transformer which includes a first coil and a second coil that is separate from the first coil; a first passive mixer which is directly connected to a first end of the second coil; and a second passive mixer which is directly connected to a second end of the second coil and is separate from the first passive mixer.

A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where n is an integer of at least 3, may be provided.

A receiving device includes: a receiver which receives a broadcast signal including an audio signal and obtains a baseband signal of a received signal; a demodulator which obtains the audio signal by demodulating the baseband signal; a middle frequency range detector which detects a signal level of a middle frequency component in a frequency range of the baseband signal; a high frequency range detector which detects a signal level of a high frequency component in the frequency range of the baseband signal; and a processing circuit which sets an effect amount of high-cut processing based on a level difference between the signal level of the middle frequency component and the signal level of the high frequency component. The receiving device further includes a high-cut filtering device which performs the high-cut processing on the audio signal in accordance with a set value of the effect amount.

A receiving device includes: a receiver which receives a broadcast signal including an audio signal and obtains a baseband signal of a received signal; a demodulator which obtains the audio signal by demodulating the baseband signal; a middle frequency range detector which detects a signal level of a middle frequency component in a frequency range of the baseband signal; a high frequency range detector which detects a signal level of a high frequency component in the frequency range of the baseband signal; and a processing circuit which sets an effect amount of high-cut processing based on a level difference between the signal level of the middle frequency component and the signal level of the high frequency component. The receiving device further includes a high-cut filtering device which performs the high-cut processing on the audio signal in accordance with a set value of the effect amount.

Disclosed is a digital stereo multiplexing-demultiplexing system based on the use of delta-sigma modulation. Creation of left (LR) and right (L+R) channels is achieved using a binary delta adder IC circuit. Delta adder is an ordinary binary adder with an interchanged role of the Sum and Carry-Out terminals. Two channel multiplexer and demultiplexer are implemented with ordinary binary logic gates. Output of the multiplexer is modulated and transmitted to the receiver where demultiplexing is performed. The proposed method can combine two or more digital stereo channels. This method is not application limited, and can be used in acoustic, video, or photo applications.

Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal and a reference signal, and generates a first differential signal and a second differential signal. The second stage circuitry receives the first differential signal and the second differential signal, and generates an output signal based on the first differential signal and the second differential signal.

A system and method for self-interference cancellation using a full duplex adaptive array includes at least four ports within the network array, with at least two transmission elements at a first port and a second port, and at least one receiving element at a third port and a fourth port. A signal is transmitted along a first network path from the two transmission elements of the first port to the receiving element of the fourth port. The signal is transmitted along a second network path from the two transmission elements of the first port to the receiving element of the third port. A weight is applied to at least one of the two transmission elements of the first port, which modifies the signal transmitted along the second network path to cancel signal interference caused by the signal at the third port during full duplex operation of the network array.