Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.

Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

An equalizer includes: a channel estimator configured to generate a set of time-domain channel coefficients based on a receive signal; a frequency-domain transformer configured to generate a set of frequency-domain channel coefficients based on a frequency transform of the set of time-domain channel coefficients; an equalizer coefficient generator configured to generate a set of frequency-domain equalizer coefficients based on the set of frequency-domain channel coefficients; a time-domain transformer configured to generate a set of time-domain equalizer coefficients based on a time transform of the set of frequency-domain equalizer coefficients; and a filter configured to filter the receive signal based on a filter function that is based on the set of time-domain equalizer coefficients.

Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.

A method is provided of receiving user data from multiple transmitters, the user data from each transmitter having been encoded as a Low Density Lattice codeword, and the multiple Low Density Lattice codewords having been transmitted so as to be received as a combined signal at a receiver, the method of receiving comprising the steps of: (i) receiving the signal, (ii) calculating coefficients of linear combinations of the codewords from the multiple transmitters, (iii) calculating a scaling factor to be applied to the signal based on the coefficients, (iv) applying the scaling factor to the signal to provide a linear combination of the codewords, (v) decoding the linear combination of the codewords based on channel state information to obtain an optimal independent linear combination of user data, (vi) repeating steps (ii), (iii) (iv) and (v) to obtain at least as many optimal independent linear combinations as the number of transmitters, and recovering the user data from the optimal independent linear combinations.

Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader such that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.

A signal sending and demodulation method, a device, and a system are provided, relate to the field of communications technologies, and can resolve a prior-art problem of a low user throughput caused by mismatch between poor PDCCH signal demodulation performance and PDSCH signal demodulation performance. A specific solution is as follows: A base station of a serving cell obtains a first power ratio restriction set preset by a base station of at least one interfering cell; sends a preset second power ratio restriction set and the first power ratio restriction set to a terminal; and sends a second original PDCCH signal to the terminal, where a current value of a second power ratio of the second original PDCCH signal is an element selected from the second power ratio restriction set. Embodiments of the present invention are used for signal demodulation.

An apparatus includes an interference rejection combining module, at least partially implemented in hardware. The interference rejection combining module determines a covariance based on a Hermitian transpose of a signal received on a subcarrier of a symbol that is not a pilot symbol.

A method and system for compensating for a doubly selective channel, and a related apparatus are applied to the field of communications technologies. In embodiments of the present invention, a receive end obtains, based on a minimum mean square error between a transmit pilot sequence and a receive pilot sequence, an optimal parameter used in a process of channel compensation and signal modulation, that is, a modulation order and a channel compensation parameter such as a channel compensation matrix. Therefore, according to the embodiments of the present invention, an optimization method is used to apply a banded equalization channel compensation method and a partial FFT transform to a communications system, thereby improving system performance.