An industrial system for controlling backplane communication, including: a cluster manager including a primary switch linked to a primary control module, at least one Input/Output, I/O, module including a secondary switch linked to a secondary control module, a unidirectional communication line linking the cluster manager to the at least one IO module through passive base plates, wherein the cluster manager includes a transmission port and a reception port on the unidirectional communication line and the at least one Input/Output module includes a reception port on the unidirectional communication line, wherein the primary control module is configured to generate a pulse via the transmission port on the unidirectional communication line, wherein, upon reception of the pulse, the primary control module is configured to create a primary timestamp from a primary clock of the primary switch and the secondary control module is configured to create a secondary timestamp from a secondary clock of the secondary switch, wherein the primary control module is configured to send a message via the transmission port on the unidirectional communication line to the secondary control module, the message including the primary timestamp, wherein, upon reception of the message, the secondary control module is configured to synchronize the secondary clock with the primary clock based on the received primary timestamp and secondary timestamp.

A method for exchanging a clock synchronization packet performed by a network apparatus, including: exchanging a clock synchronization packet with a first clock source, where the network apparatus includes a boundary clock; determining a first time deviation of the boundary clock relative to the first clock source according to the clock synchronization packet exchanged with the first clock source, where the boundary clock avoids performing an operation of calibrating a time of a local clock of the boundary clock according to the first time deviation; and sending a clock synchronization packet to a first slave clock of the boundary clock, where the clock synchronization packet includes a first timestamp, a value of the first timestamp is equal to a first corrected value, and the first corrected value is a value obtained by the boundary clock by correcting the time of the local clock by using the first time deviation.

An electronic eyewear device includes first and second systems-on-chip (SoCs) having independent time bases. The first and second SoCs are connected by a shared general purpose input/output (GPIO) connection and an inter-SoC interface. The first and second SoCs are synchronized to each other by the first SoC asserting the shared GPIO connection to the second SoC where assertion of the message to the shared GPIO connection triggers an interrupt request (IRQ) at the second SoC. The first SoC records a first timestamp for assertion of the message to the GPIO connection, and the second SoC records a second timestamp of receipt of the IRQ. The first SoC sends a message including the first timestamp to the second SoC over the inter-SoC interface. The second SoC calculates a clock offset between the first and second SoCs as a difference between the first and second timestamps.

An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases and an inter-SoC interface that connects the first and second SoCs. The operations of the first and second SoCs are synchronized by aligning the time bases for the SoCs using a modified PTP technique. The technique includes the second SoC receiving a time synchronization message from the first SoC over the inter-SoC interface, recording a local timestamp of receipt of the time synchronization message, receiving a master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the time synchronization message by the first SoC, and calculating a time offset between the local timestamp and the master timestamp. The time bases of the first SoC and second SoC are then aligned using the calculated time offset. To account for transmission delays, multiple time offsets may be averaged.

Techniques are described for reconciling events timestamped in different time domains in multi-node systems supporting low-latency hardware timestamping. First and second nodes having independent time bases are synchronized by the first node generating an event that is received effectively simultaneously at the first and second nodes, the first and second nodes recording a timestamp of receipt of the event, the first node asynchronously querying the second node for its timestamp of receipt of the event and comparing its timestamp of receipt of the event with the timestamp of receipt of the event by the second node, and the first node using a difference in the timestamps of receipt of the event by the first and second nodes to align the time bases of the first and second nodes. The nodes may include hardware timestamping functionality or use an external component (e.g., field programmable gate array) to provide the timestamping functionality.

There is provided a method and device for forwarding a digital signal arranged into portions that each contain a timestamp and an error detection code. Duplicates of the digital signal are received on a first optical path and a second, separate optical path. Corresponding timestamps are identified in the signals and used to synchronize corresponding portions of the signals. The error detection codes in the synchronized portions are used to allow one and only one of the corresponding portions to be selected for forwarding. The selected portions are then forwarded.

In one embodiment, an event processing system includes a clock configured to provide time values, and event processing circuitry, which is configured to generate a confidence level indicative of a degree of confidence of an accuracy of a timestamp, the timestamp being generated for an event responsively to a time value indicative of when an operation associated with the event occurred.

A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.

A method for implementing a distributed boundary clock in situations where book-end devices such as microwave TX/RX pairs must collaborate in achieving PTP on-path support is described. A dedicated channel, generally low-speed compared to the main channel is used to transfer timing from the master side to the slave side using framing and super-framing applied to the digital channel. Time-stamps of events such as super-frame boundaries are communicated between the two sides to enable timing transfer.

An operation method of a first communication node in an Ethernet-based vehicle network includes identifying a link status between the first communication node and each of a plurality of communication nodes included in the vehicle network; receiving a first frame from a second communication node whose link status is normal among the plurality of communication nodes; identifying a first time difference between a local time of the first communication node and a time stamp of the first frame; and determining a synchronization error between the first communication node and the second communication node based on the first time difference.