A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

A communication system and a communication method for one-way transmission are provided. The communication method includes: receiving, by a router, a first synchronization message from a grandmaster clock; generating, by the router, a timestamp according to the first synchronization message; receiving, by the router, at least one data packet; transmitting, by the router, the at least one data packet and the timestamp to a programmable logic device; and outputting, by the programmable logic device, the at least one data packet and the timestamp.

This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

Disclosed herein to a method and apparatus for synchronizing signals. According to an embodiment of the present disclosure, there is provided a method for synchronizing a signal. The method comprising: receiving a reference time and performing time synchronization with the reference time; calculating a clock frequency of a system clock based on the reference time; and generating a sampling clock by using the calculated clock frequency of the system clock and a preset sampling frequency.

Time transfer systems and methods implemented in a first node steps of communicating a stream of encoded blocks with a second node; and communicating synchronization messages with the second node via a synchronization message channel in overhead associated with the stream of encoded blocks, wherein the synchronization messages are utilized for synchronization of a clock at the second node. Each block in the stream of encoded blocks can be one of a data block and an overhead block.

The present disclosure provides an on-board synchronization device. The on-board synchronization device includes: a first circuit and at least one second circuit. The first circuit is configured to receive an initial signal containing Universal Time Coordinated (UTC), generate a first signal containing the UTC, and output the first signal to at least one on-board device, such that the at least one on-board device synchronizes its built-in clock with the UTC based on the first signal. The second circuit is configured to receive a Pulse Per Second (PPS) signal, generate a periodic second signal with a same phase as the PPS signal, and output the second signal or the PPS signal to the at least one on-board device, such that the at least one on-board device performs a predetermined action based on the second signal or the PPS signal.

A controller includes circuitry configured to: synchronize a master clock with an external global clock and set a master time based on the master clock; synchronize a controller clock with the master clock and perform time synchronization to synchronize a controller time based on the controller clock with the master time; transmit controller time data indicating the synchronized controller time to at least one local device; set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal for the time synchronization; determine whether one clock cycle of the plurality of clock cycles has started within one time window of the plurality of time windows, the one time window corresponding to the one clock cycle; and suspend the time synchronization corresponding to the one clock cycle, in response to determining that the one clock cycle has not started within the one time window.

There is provided a method and device for forwarding a digital signal arranged into portions that each contain a timestamp and an error detection code. Duplicates of the digital signal are received on a first optical path and a second, separate optical path. Corresponding timestamps are identified in the signals and used to synchronize corresponding portions of the signals. The error detection codes in the synchronized portions are used to allow one and only one of the corresponding portions to be selected for forwarding. The selected portions are then forwarded.

A service data processing method and apparatus is disclosed. A data frame is divided into code blocks with smaller granularity, and service data is mapped to a corresponding quantity of code blocks in the data frame based on a service requirement. In addition, the data frame is used to indicate a location of a code block carrying the service data. In one manner, a code block in a payload area of the data frame is divided into a data code block and an overhead code block, and the overhead code block is used to indicate a location of a data code block carrying the service data. In the another manner, an indication field is configured in an overhead area of the data frame to indicate a location of a code block that carries the service data and that is in the payload area of the data frame.