A method of transmitting packets between a plurality of nodes of a network. The method comprising in each of a plurality of data timeslots, transmitting a data packet with one of the plurality of nodes and listening to receive the data packet with the remainder of the plurality of nodes. The method further comprising in each of one or more parity timeslots following the plurality of data timeslots, transmitting a parity packet with one or more of the plurality of nodes and listening to receive the parity packet with the remainder of the plurality of nodes. Each parity packet is derived from a set of the data packets transmitted during the plurality of data timeslots.

Systems and methods are disclosed herein for performing a time-ordered operation on messages transmitted from multiple sources to a region of networked machines. In an embodiment, the system runs a software-based synchronization process to synchronize each of a plurality of gateways with a reference clock, where each gateway is a machine on a perimeter of the region of networked machines and is connected to receive messages from multiple sources. The system receives messages that enter the region through one of the gateways, where the gateway timestamps the message. The system then performs the time-ordered operation on the received messages in an order based on an absolute time of entry into the region, where the absolute time of entry is relative to the reference clock and is determined based on the timestamp from the gateway.

Techniques are described to provide for re-timing a packetized radio flow to clean noise induced by packet delay variation of a packet network. In one example, a method includes receiving, at a first node of a fronthaul network, a Radio over Ethernet (RoE) frame transmitted by a second node in which the RoE frame comprises a Common Public Radio Interface (CPRI) bit stream associated with a first radio device, a sequence number, and a first time stamp. The method may further include generating a second time stamp by the first node upon obtaining the RoE frame; calculating an induced delay value based, at least in part, on the first time stamp and the second time stamp; calculating a re-timing value based on a re-timing interval and the induced delay value; and transmitting the CPRI bit stream to a second radio device based on the re-timing value.

Systems and methods are disclosed herein for performing a time-triggered distribution of messages from a region of networked machines to multiple destinations. In an embodiment, the system runs a software-based synchronization process to synchronize each of a plurality of gateways with a reference clock, wherein each gateway is a machine on a perimeter of the region of networked machines and is connected to transmit messages to multiple destinations. The gateways receive messages from within the region of networked machines for distribution to multiple destinations outside the region of networked machines according to a distribution schedule based on absolute time relative to the reference clock. The gateways perform the distribution of received messages, wherein each gateway determines absolute time based on that gateway's synchronization with the reference clock.

Systems and methods are disclosed herein for performing a time-ordered operation on messages transmitted from multiple sources to a region of networked machines. In an embodiment, the system runs a software-based synchronization process to synchronize each of a plurality of gateways with a reference clock, where each gateway is a machine on a perimeter of the region of networked machines and is connected to receive messages from multiple sources. The system receives messages that enter the region through one of the gateways, where the gateway timestamps the message. The system then performs the time-ordered operation on the received messages in an order based on an absolute time of entry into the region, where the absolute time of entry is relative to the reference clock and is determined based on the timestamp from the gateway.

A method for TDMA slot synchronization and calibration of a master and a slave includes: receiving a synchronizing frame from the master by the slave, wherein the synchronizing frame includes a first count value of a timing counter of the master; analysing the synchronizing frame by the slave to acquire the first count value; and adjusting a TDMA slot of the slave according to the first count value and a second count value of a timing counter of the slave to synchronize the TDMA slot of the slave with a TDMA slot of the master.

A battery powered node within a wireless mesh network maintains a mapping between temperature and oscillator drift and compensates for oscillator drift based on this mapping. When the mapping includes insufficient data points to map the current temperature to an oscillator drift value, the battery powered node requests calibration packets from an adjacent upstream node in the network. The adjacent node transmits two calibration packets with a transmit time delta and also indicates this time delta in the first calibration packet. The battery powered node receives the two calibration packets and measures the receive time delta. The battery powered node compares the transmit time delta to the receive time delta to determine oscillator drift compared to an oscillator in the adjacent node. The battery powered node then updates the mapping based on the current temperature and determined oscillator drift.

A bus system, a method for operating a bus system and a participant of a bus system are provided. The participant includes a timer and a transceiver circuit. The transceiver circuit is configured to receive a data packet having a time stamp value via a bus. The timer is configured for synchronization, based on the time stamp value. The timer is configured to change the time stamp value. The transceiver circuit is configured to transmit the data packet with the changed time stamp value via the bus.

A time synchronization method, a programmable logic device, a single board and a network element are provided. In the method, a programmable logic device receives a request message from a terminal, generates a time synchronization message according to the request message, and sends the time synchronization message to the terminal.

Methods and circuitry for relatively low-speed bus time stamping and triggering for use in acoustic object and gesture detection and recognition are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that includes a data line and a clock line. The master device generates and controls a clock signal on the clock line and sends a synchronization command over the data line to the slave devices. The master device receives timestamp and/or other information corresponding to events detected at each slave device, such as a detected acoustic wave reflected from an object. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can use the event times to derive positions and gestures associated with detected objects.