A method for making IEEE 1588 master clock configuration for an ONU in a PON includes creating a PTP port on a UNI of the ONU, and generating a corresponding PTP port ME for the PTP port to indicate that the UNI is operating in a master clock mode; generating a 1588 master clock configuration data ME based on PTP port MEs of all PTP ports in the ONU, to store profiles of all PTP ports used as master clock devices; and generating a clock data set ME according to the 1588 master clock configure data ME, to indicate clock source information of all PTP ports used as master clock devices.

Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.

A method and apparatus for controlling delay over a data path in a device for transporting Ethernet packets over an optical transport network. The device is configured to receive an incoming clock signal having a first frequency and an incoming data signal and to output an outgoing clock signal having a second frequency and an outgoing data signal. One or more delays over the data path in the device are measured in a predetermined measurement period. A phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop in such a way that the delay over the data path in the device is substantially equal to a fixed delay value.

A real-time Ethernet (RTE) protocol includes start-up frames originated by a master device for network initialization including a preamble, destination address (DA), source address (SA), a type field, and a status field including state information that indicates a current protocol state that the Ethernet network is in for the slave devices to translate for dynamically switching to one of a plurality of provided frame forwarding modes. The start-up frames include device Discovery frames at power up, Parameterization frames that distribute network parameters, and Time Synchronization frames including the master's time and unique assigned communication time slots for each slave device. After the initialization at least one data exchange frame is transmitted exclusive of SA and DA including a preamble that comprises a header that differentiates between master and slave, a type field, a status field excluding the current protocol state, and a data payload.

An audio system, method, and computer program product for synchronizing device clocks. The systems, methods and computer program product can establish a first isochronous data stream between a peripheral device and a first device and establish a second isochronous data stream between the first device and a second device to send data between the first and second device. As the two data streams may rely on two different device clocks, e.g., one clock which defines the timing for the first isochronous data stream and a second clock which defines the timing for the second isochronous data stream, the systems, methods, and computer program disclosed herein are configured to maintain synchronization and/or synchronize the first clock with the second clock to prevent data loss due to clock drift.

An apparatus for controlling an automated installation has a first controller and a second controller that are connected to one another via a communication network. The first and second controllers each have a local clock and execute control tasks. The first and second controllers each further have a synchronization service that is used to synchronize the respective local clocks to a common reference clock. A timer repeatedly sends a trigger message to the first and second controllers. Each of the two controllers, on receiving the trigger message, determines a local time. The controllers interchange the respective local time and each compute a difference between their own local time and the local time obtained from the other controller. On the basis of the difference, each of the two controllers controls a local actuator.

The present invention achieves, using simple circuits, timing synchronization among ECUs of an electronic control device which is configured from a driver ECU, a sensor ECU, and an integrated ECU which are connected over a network. This electronic control device is provided with a driver ECU for driving various loads for vehicular control, a sensor ECU for sampling various sensor signals, and an integrated ECU which is connected to the driver ECU and sensor ECU over a network and calculates command values to the various loads in accordance with various sensor data, the electronic control device being characterized in that the driver ECU has timer D for generating internal timing, the sensor ECU has timer S for generating internal timing, and the integrated ECU has timer M serving as a reference for timer D and timer S.

A method and apparatus for controlling delay over a data path in a device for transporting Ethernet packets over an optical transport network. The device is configured to receive an incoming clock signal having a first frequency and an incoming data signal and to output an outgoing clock signal having a second frequency and an outgoing data signal. One or more delays over the data path in the device are measured in a predetermined measurement period. A phase adjustment amount is determined based on the one or more measured delays over the data path in the predetermined measurement period, and based on the determining phase adjustment amount, a phase of the outgoing clock signal is adjusted by a phase locked loop in such a way that the delay over the data path in the device is substantially equal to a fixed delay value.

A time synchronization method, a programmable logic device, a single board and a network element are provided. In the method, a programmable logic device receives a request message from a terminal, generates a time synchronization message according to the request message, and sends the time synchronization message to the terminal.

A transport network (20) is connected to a first wireless base station (3, 4) and to a second wireless base station (6). The first wireless base station comprises a remote radio unit (3) and a baseband processing unit (4) which are connected by the transport network (20). A node (16) of the transport network (20) receives a synchronous time division multiplexed communication signal which carries at least a first communication signal between the baseband processing unit (4) and the remote radio unit (3). The node (16) determines a frequency synchronisation signal from the synchronous time division multiplexed communication signal. The node (16) transmits the synchronous time division multiplexed communication signal to the remote radio unit (3) of the first wireless base station. The node (16) transmits the frequency synchronisation signal to the second wireless base station (6). The node (16) also assists with providing phase/time synchronisation to the second wireless base station (6).