Embodiments include systems and methods for implementing a multi-rate FIR by using rate-dependent bit stuffing on the cursor, while using rate-independent (e.g., full-rate) spacing on the pre- and post-cursor. For example, in the FIR data path, the cursor bit output is generated using bit stuffing, depending on a selected rate mode (e.g., full-rate, half-rate, quarter-rate, eighth-rate, etc.), but the spacing of the pre-cursor, cursor, and post-cursor are maintained at 1 UI apart (i.e., the full-rate spacing) for all rate modes. Such an approach can appreciably reduce complexity of the logic and can appreciably relieve the critical timing path.

To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

The present invention reduces the degradation in performance of one or more radio signals that are co-transmitted with a first radio signal from the same transmitting antenna in the same frequency channel and received by the same antenna due to multipath or other shared interference, where the one or more radio signals can be separated from the first radio signal. All received signals are coupled to the same adaptive array or adaptive filter to reduce multipath or other shared interference of the first radio signal, which reduces multipath and other shared interference in the other radio signals before they are separated and processed by their respective receivers, or the individual radio signals are separated before the first signal enters the adaptive array and coupled to a slave weighting network slaved to the weights of the adaptive array of the first signal to reduce interference in all the signals.

A method of equalization for high-speed processing and an equalizer thereof are proposed. The method of equalization includes determining a filter coefficient applied to a transmitter equalizer provided with a 2-tap precoder according to an approximate channel response characteristic, generating a pre-equalization signal by removing precursor ISI of a transmission feedback signal by the precoder to which the filter coefficient is applied, so as to output the pre-equalization signal as a transmitting signal, and receiving a transmission signal and generating an equalization signal by removing postcursor ISI of the received transmission signal by a receiver equalizer provided with a feedback filter having auxiliary coefficients for compensating for a difference between an overall channel response of the transmission signal and a channel response based on the precoder.

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

The present invention reduces the degradation in performance of one or more radio signals that are co-transmitted with a first radio signal from the same transmitting antenna in the same frequency channel and received by the same antenna due to multipath or other shared interference, where the one or more radio signals can be separated from the first radio signal. All received signals are coupled to the same adaptive array or adaptive filter to reduce multipath or other shared interference of the first radio signal, which reduces multipath and other shared interference in the other radio signals before they are separated and processed by their respective receivers, or the individual radio signals are separated before the first signal enters the adaptive array and coupled to a slave weighting network slaved to the weights of the adaptive array of the first signal to reduce interference in all the signals.

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

An analog delay cell is provided that includes a transconductance-capacitance stage and an inductive transimpedance amplifier stage that provides an all-pass transfer function. In another embodiment, an adaptive analog delay cell including a transconductance (gm) plus capacitance (C) stage and an inductive-capacitance transimpedance amplifier (TIA) stage with digitally programmable phase-shift is provided. The adaptive analog delay cell increases the phase-shift by incorporating an LC network in the feedback path of the transimpedance stage. The disclosed analog delay cells can be used to provide delays in a tapped delay line. Also, the disclosed analog delay cells may be used to perform the multiplier and summation functions of a tapped delay line in addition to providing the delays. In another embodiment, the transimpedance amplifier stage includes an inductive-capacitive transimpedance amplifier stage.