The invention comprises a method for controlling a gain of a multi-stage equalizer of a serial data receiver, applied to the serial data receiver comprising the multi-stage equalizer, wherein the method comprises: Step S1, enabling the serial data receiver to receive a set of serial data; Step S2, selecting a plurality of continuous data sequences from the set of serial data according to a preset first rule; Step S3, extracting a predetermined bit from each of the plurality of continuous data sequences; Step S4, calculating an equalization gain identifier corresponding to each of the plurality of continuous data sequences according to a predetermined bit in each of the plurality of continuous data sequences; Step S5, obtaining an optimized equalization gain identifier through calculation according to each of the equalization gain identifiers; and Step S6, controlling a gain value of the multi-stage equalizer according to the optimized equalization gain identifier.

A passive continuous time linear equalizer (CTLE) includes an alternating current (AC) coupling capacitor coupled in series between an input node and an output node of the passive equalizer. An electrostatic discharge protection device is coupled in parallel to the input node. An inductor is coupled in parallel to a node between the input node and the output node. Further, the passive CTLE includes a variable resistor coupled in series between the inductor and a ground. Increased impedance of the inductor at higher frequencies portions of the input signal operate to boost a gain of the equalizer at the higher frequencies without active power by over-terminating the input signal.

A method includes receiving an n-level Pulse Amplitude Modulated (PAM-n) signal at a receiver from a transmitter via a channel. The method also includes determining one or more sampling times of the PAM-n signal. The method further includes determining one or more slicing levels of the PAM-n signal. The method also includes extracting and decomposing jitter in the PAM-n signal for each slicing level of the PAM-n signal to determine one or more jitter components. The method further includes extracting and decomposing noise in the PAM-n signal for each data level of the PAM-n signal to determine one or more noise components. The method also includes adjusting the receiver, the transmitter, the channel, or any combination thereof, based on the one or more jitter components, the one or more noise components, or both.

A wire-line transceiver is configured to perform a serial loop back test. The wire-line transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver. The fractional FFE circuit is configured to induce a delay one of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.

High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

A method facilitates determining transmission loss in a transmission signal and adjusting a receiver setting of a receiver to compensate for the transmission loss. The method includes transmitting a transmission signal from a transmitter and receiving the transmission signal by a first receiver and a second receiver. The method includes digitizing the transmission signal by the first receiver at a first sampling frequency and digitizing the transmission signal by the second receiver at a second sampling frequency that is less than or equal to the first sampling frequency. The method includes generating a PAM-n eye diagram of the transmission signal by the second receiver using digitized signals digitized by the first and second receivers and adjusting an equalizer setting of a first equalizer of the first receiver using eye-opening information of the PAM-n eye diagram where the eye-opening information includes information for the transmission loss.

A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.

An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

A continuously or step variable passive noise filter for removing noise from a signal received from a DUT added by a test and measurement instrument channel. The noise filter may include, for example, a splitter splits a signal into at least a first split signal and a second split signal. A first path receives the first split signal and includes a variable attenuator and/or a variable delay line which may be set based on the channel response of the DUT which is connected. The variable attenuator and/or the variable delay line may be continuously or stepped variable, as will be discussed in more detail below. A second path is also included to receive the second split signal and a combiner combines a signal from the first path and a signal from the second path into a combined signal.

A method for receiving a signal and for rejecting interference in a multichannel receiver, comprises the steps of: reception, transposition and discretization of the signal received on each of the channels of the receiver, so as to obtain a discretized multichannel signal, synchronization of the discretized multichannel signal, computation, on the basis of the discretized and synchronized multichannel signal, of a matrix {circumflex over (R)} of correlation of the total noise, computation, on the basis of the matrix {circumflex over (R)} of correlation of the total noise, of a vector w comprising amplitude phase weighting coefficients of a multichannel filter, and application, to the discretized and synchronized multichannel signal, of a multichannel filtering processing on the basis of the vector w, and then of a single-channel equalization processing to the filtered signal.