A method of realization of adaptive equalization and an adaptive equalizer. The adaptive equalizer comprises an equalizer unit, which is used for equaling an input signal according to a compensation coefficient to obtain an output signal; a sampling comparison unit, which is connected to an output of the equalizer and is used for sampling a comparison result of the output signal of the equalizer and a reference voltage corresponding to reference voltage step; a data processing unit, which is connected to the sampling comparison unit and the equalizer unit. It is used for scanning a reference voltage step to determine range of the reference voltage steps to which step the amplitude of the output signal is corresponding; and scanning a compensation coefficient step, and determining the compensation coefficient for equalization according to the range of reference voltage steps. The solution of the present invention resolves such problems as long adaptive adjustment time, algorithm complex and large power consumption of the existing self-adaptive equalization algorithm.

receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuit configured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.

A test and measurement instrument has one or more input ports to connect the instrument to a device under test (DUT), one or more processors configured to execute code to cause the one or more processors to: receive an equalized waveform and an un-equalized waveform through the input port from the DUT, without any knowledge of a digital pattern that corresponds to the waveforms and without extracting the digital pattern from the waveforms, align the un-equalized waveform and the equalized waveform in time to produce an aligned un-equalized waveform and an aligned equalized waveform, and use the aligned equalized waveform and the aligned un-equalized waveform to determine equalizer tap values.

A serial data receiver is disclosed. In one embodiment, a receiver includes an amplifier circuit configured to receive one or more signals that encode a serial data stream that includes a plurality of data symbols and to perform a comparison of the one or more signals to a threshold value to generate a recovered data symbol. The receiver circuit further includes a threshold circuit configured to generate a delayed version of the one or more signals. The threshold circuit is further configured to generate a delayed data symbol using the delayed version of the one or more signals and adjust the threshold value using the delayed data symbol.

The present invention is directed to communication method and techniques. In a specific embodiment, the present invention provides a receiver that interleaves data signal n-ways for n slices. Each of the n slices includes feedforward equalizer and decision feedback equalizers that are coupled to other slices. Each of the n slices also includes an analog-to-digital converter section that includes data and error slicers. There are other embodiments as well.

This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

A receiver for a passive optical network is provided. The receiver includes an analog-to-digital converter circuitry configured generate a digital receive signal based on an analog receive signal. The analog receive signal is based on an optical receive signal encoded with a binary transmit sequence. The receiver additionally comprises linear equalizer circuitry configured to generate an equalized receive signal by linearly equalizing the digital receive signal. Further, the receiver comprises secondary equalizer circuitry configured to generate soft information indicating a respective reliability of elements in the equalized receive signal using the Viterbi algorithm. In addition, the receiver comprises decoder circuitry configured to generate a digital output signal based on the soft information using soft decision forward error correction.

A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable/disable vector Q[1:N] that can turn on/off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

A receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuit configured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.