An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

receiver may include a first filter configured to generate a first estimation of a symbol of a received signal and a second filter configured to generate a second estimation of the symbol of the received signal. The receiver may also include a decoder configured to decode the symbol using one of the first estimation and the second estimation and a decision circuit configured to select one of the first estimation and the second estimation to provide to the decoder for decoding of the symbol based on a comparison of the first estimation to an estimation threshold.

A transmission apparatus (10) according to the present disclosure incudes: a correction value calculation unit (130) configured to calculate a correction value for correcting an initial standby time of a direct wave signal or an indirect wave signal based on a reception time of the direct wave signal and a reception time of the indirect wave signal that follows the direct wave signal, and a transmission time fluctuation compensation unit (140) configured to calculate the standby time by correcting the initial standby time using the correction value and cause the direct wave signal or the indirect wave signal to stand by in accordance with the standby time. The correction value calculation unit (130) calculates a correction value for increasing the standby time of the direct wave signal or reducing the standby time of the indirect wave signal.

A system for controlling equalization applied to a received signal comprising an equalizer configured to equalize on a received signal to generate an equalized signal, and a clock recovery module configured to recover a clock signal from the equalized signal or the received signal. A clock adjustment system is configured to receive the clock signal, and at least one control signal, to create a sampling clock signal. A filter is configured to filter the equalized signal to create a filtered signal. A sampling unit samples the filtered signal or the equalized signal such that the output of the sampling unit is provided to a controller. The controller is configured to receive and process the output of the sampling unit to generate a boost signal, and the controller is further configured to provide the boost signal to the equalizer to control the amount of equalization performed by the equalizer.

A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

One example includes an equalizer system. The system includes a filter system configured to receive digital sample blocks associated with an input signal and to provide equalized digital sample blocks associated with the respective digital sample blocks based on adaptive tap weights. Each of the digital sample blocks includes samples and each of the equalized digital sample blocks includes equalized samples. The system also includes a sample set selector to select a subset of equalized samples from each of the equalized digital sample blocks at the output of the filter and an error estimator configured to implement an error estimation algorithm on the subset of the equalized samples to determine a residual error associated with the equalized samples. The system further includes a tap weight generator configured to generate the adaptive tap weights in response to the residual error and to provide the adaptive tap weights to the filter.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.