H04L25/03057

Signal receiving device

A signal equalization method includes: receiving a clock signal and a first reference signal; detecting a phase and a frequency of the clock signal based on the first reference signal to generate a detection result; generating a speed judgement signal according to the detection result; and, receiving the speed judgement signal and deciding an equalizer operation parameter according to the speed judgement signal.

METHODS AND SYSTEMS FOR IMPROVING COMMUNICATION USING AN ALTERNATE LINK
20170331644 · 2017-11-16 ·

A method and system for maximizing throughput and minimizing latency in a communication system that supports heterogeneous links is presented. The communication system supports a primary link and an alternate link, and the method and system leverage the alternate link to reduce the overhead transmitted over the primary link, thereby increasing throughput and reducing end-to-end latency. The higher latency alternate link provides a delayed version of an information signal that corresponds to a portion of the information signal that is transmitted on the primary link. The received samples from the primary and alternate links may be used to equalize subsequent portions of the information signal received over the primary link, and may also be used for synchronization, timing recovery, DC offset removal, I/Q imbalance compensation, and frequency-offset estimation.

OFFSET DETECTOR CIRCUIT FOR DIFFERENTIAL SIGNAL GENERATOR, RECEIVER, AND METHOD OF COMPENSATING FOR OFFSET OF DIFFERENTIAL SIGNAL GENERATOR

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

CONTINUOUS TIME LINEAR EQUALIZATION AND BANDWIDTH ADAPTATION USING PEAK DETECTOR
20220360475 · 2022-11-10 ·

Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.

CLOCK DATA RECOVERY WITH DECISION FEEDBACK EQUALIZATION
20170317859 · 2017-11-02 ·

Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error indication, the phase error indication selected in response to identification of a predetermined data decision pattern.

Circuits and methods for DFE with reduced area and power consumption

A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

System and method for generating spreaded sequence with low peak-to-average power ratio (PAPR) waveform
11489707 · 2022-11-01 · ·

Embodiments of the present disclosure relate to a method and system to generate a waveform in a communication network. The transmitter receives an input data and transmit a generated waveform to another communication system. The input data is spread with a spread code to generate a spread data and rotated using a constellation rotation operation to produce a rotated data. The rotated data is then precoded using precoding filter to produce a precoded data, and transformed into DFT output data using DFT operation. The DFT output data is then mapped with subcarriers to generate the sub-carrier mapped DFT data and modulated using Orthogonal Frequency Division Multiplexing (OFDM) modulation to generate the waveform with low PAPR.

Q-BASED ZERO-FORCING ADAPTIVE CONTROL
20170310510 · 2017-10-26 · ·

A method of adaptive control is provided. The method may include measuring a first set of average sign values of inter-symbol interference (ISI) of an output signal with a set of control parameters using correlation. The method may further include determining a first set of Q values. The method may also include adjusting the set of control parameters based on the first set of Q values. The method may include measuring a second set of average sign values of ISI using inverted correlation. The method may further include determining a second set of Q values. The method may also include determining a difference between the first set of Q values and the second set of Q values. The method may further include adjusting the set of control parameters based on the difference between the first set of Q values and the second set of Q values. The method may further include adjusting the output signal based on the set of control parameters.

Multiplexer loop architecture for decision feedback equalizer circuits
09800435 · 2017-10-24 · ·

Circuits, devices, methods for decision feedback equalization are described. A decision feedback circuit can include L N-tap decision feedback equalizer (DFE) branch input lines and an unfolding multiplexer array network. The network is configured to generate at least one unfolded output based on inputs from a subset of the branch input lines and includes a plurality of multiplexer arrays wherein outputs from a first multiplexer array in the plurality of multiplexer arrays are connected to selection lines of a second multiplexer array in the plurality of multiplexer arrays.

Linear Equalization For Use In Low Latency High Speed Communication Systems

A communication system including a transmitter and a receiver is disclosed. The transmitter transmits frames, at least two consecutive frames containing different training sequences. The receiver receives data communicated from the transmitter over a channel. The receiver combines and jointly processes the at least two consecutive frames transmitted by the transmitter to estimate a channel state of the channel.