Systems and methods are provided for utilizing low gain low noise signal amplification and ideal taps in coaxial networks. An ideal tap configured for use in coaxial networks may have a plurality of ports, one or more processing circuits configured for handling reception and transmission of signals communicated via the tap, and one or more echo cancellation circuits configured for providing echo cancellation during operations of the tap. The processing circuits are configured based on particular predefined tap performance criteria. The tap performance criteria may relate to one or more of port-to-port isolation, return loss, port-to-port gain, and up-tilt. The echo cancellation circuits may be configurable for providing the echo cancellation based on the tap performance criteria. The echo cancellation circuits may include an echo cancellation control circuit for controlling echo cancellation functions and/or operations. The echo cancellation circuits may include dedicated per-port echo cancellation circuits.

In a nonlinear signal filtering system, a signal having a series of signal samples is filtered. The signal samples are affected by interactions with adjacent signal samples and nonlinear distortions. The system contains a series of alternating linear system elements and nonlinear system elements that are used for mitigation of distortion resulting from the nonlinear distortions with memory effects. The linear system elements can scale each signal sample in the series of signal samples by scaling parameters and sums a plurality of consecutive scaled signal samples, and the nonlinear system elements can transform the output of the linear system elements according to instantaneous nonlinear functions.

The present disclosure relates to a 1/K-rate decision feedback equalizer (DFE) and to a decision feedback equalization method. The DFE comprises: (i) a summing circuit configured to combine K intersymbol interference (ISI) cancellation signals with an input signal of the DFE, (ii) K branches each including a reset-to-zero (RZ) latch configured to receive an output signal of the summing circuit according to a clock signal and to produce a RZ signal, and (iii) a feedback circuit including K filters each configured to receive a respective RZ signal from a respective RZ latch and to produce a respective ISI cancellation signal. The method comprises: (i) producing an output signal for K branches based on K cancellation signals and on an input signal, (ii) producing K RZ signals based on the output signal and on a clock signal, and (iii) producing the K ISI cancellation signals based on the K RZ signals.

An apparatus for equalizing a digital input signal is provided. The apparatus includes an input node configured to receive the digital input signal. Further, the apparatus includes a plurality of filters coupled in parallel to the input node. The plurality of filters are configured to filter the digital input signal and generate a respective filtered signal. Additionally, the apparatus includes a combiner circuit coupled to the plurality of filters. The combiner circuit is configured to receive the respective filtered signal from the plurality of filters, and to generate an equalized signal by combining the received filtered signals according to a non-linear equalization function.

In a nonlinear signal filtering system, a signal having a series of signal samples is filtered. The signal samples are affected by interactions with adjacent signal samples and nonlinear distortions. The system contains a series of alternating linear system elements and nonlinear system elements that are used for mitigation of distortion resulting from the nonlinear distortions with memory effects. The linear system elements can scale each signal sample in the series of signal samples by scaling parameters and sums a plurality of consecutive scaled signal samples, and the nonlinear system elements can transform the output of the linear system elements according to instantaneous nonlinear functions.

Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.