Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information.

The present invention provides a multi-rate bidirectional transmission system. A sending device and a receiving device transmit data in a bidirectional way through a cable. The multi-rate bidirectional transmission system communicates with a reverse configuration packet by sending a forward configuration packet at a preset rate in a time-division manner, selects a serial rate jointly supported by the sending device and the receiving device, and selects a training sequence length. Then, the sending device and the receiving device perform equalization training at the selected serial rate with the selected training sequence length, thus avoiding searching the serial rate and presetting the training sequence length in the worst case, thus simplifying the design and improving the link training speed.

Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

A PAM4 receiver including an adaptive continuous-time linear equalizer and a method for training the same are disclosed. The PAM4 receiver and the method for training the same of the present invention employs a training pattern including a first training data pattern and second training data pattern to adaptively tune the PAM4 receiver to achieve accurate data reception and long-distance, high-speed communication.

The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include determining, using a decision feedback equalization (“DFE”) training block, a voltage value for one or more resistor values. Embodiments may further include determining, using the DFE training block, a voltage value for one or more capacitor values and identifying a voltage difference between the voltage value for one or more resistor values and the voltage value for one or more capacitor values. Embodiments may further include iteratively performing the determining of the voltage value and identifying of the voltage difference for each of the plurality of capacitor values until the voltage difference is at one or more minimum values to generate one or more optimal resistor and capacitor coefficients for a continuous time linear equalization filter.