H04L25/03133

DETERMINING A COMPOSITE ZERO-FORCING EQUALIZER
20240243950 · 2024-07-18 ·

Apparatuses, methods, and systems are disclosed for determining a composite zero-forcing equalizer. One method includes measuring a first frequency response at a first antenna connector. The method includes determining a first zero-forcing equalizer for the first antenna connector as an inverse of the first frequency response. The method includes measuring a second frequency response at a second antenna connector. The method includes determining a second zero-forcing equalizer for the second antenna connector as an inverse of the second frequency response. The method includes determining a composite zero-forcing equalizer as a normalized power weighted linear combination of absolute value magnitudes of the first zero-forcing equalizer and the second zero-forcing equalizer.

EXTENDED LINK-TRAINING TIME NEGOTIATED ON LINK START-UP
20240243951 · 2024-07-18 · ·

Examples described herein relate to link training between network connected devices. In some examples, an amount to extend link training is determined. The amount to extend link training can be determined by: receiving, by a receiver in a first device, signals over a lane from a transmitter in a second device, the signals indicating capability to extend link training time and amount to extend link training time; determining, at the first device, a link training time based on a default link training time and an amount to extend link training time; and performing link training based on the determined link training time. In some examples, the determined amount is highest common denominator of the received identified capability and transmitted indicated capability.

MULTILEVEL DRIVER FOR HIGH SPEED CHIP-TO-CHIP COMMUNICATIONS
20190028307 · 2019-01-24 ·

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

METHOD AND NODE IN A WIRELESS COMMUNICATION NETWORK
20190020512 · 2019-01-17 ·

Transmitting device for a wireless communication system and method therein for transmitting data. The transmitting device comprises a processor, configured to: obtain a channel response (h); determine pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2) of a pre-processor structure, based on the obtained channel response (h); and pre-process the data, based on the pre-processor structure and the determined pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2). The transmitting device comprises a transmitter, configured to transmit the pre-processed data.

PAM-4 DFE architectures with symbol-transition dependent DFE tap values

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

EQUALIZER AND METHOD FOR EQUALIZING A RECEIVE SIGNAL

An equalizer includes: a channel estimator configured to generate a set of time-domain channel coefficients based on a receive signal; a frequency-domain transformer configured to generate a set of frequency-domain channel coefficients based on a frequency transform of the set of time-domain channel coefficients; an equalizer coefficient generator configured to generate a set of frequency-domain equalizer coefficients based on the set of frequency-domain channel coefficients; a time-domain transformer configured to generate a set of time-domain equalizer coefficients based on a time transform of the set of frequency-domain equalizer coefficients; and a filter configured to filter the receive signal based on a filter function that is based on the set of time-domain equalizer coefficients.

Multi-stage equalisation method and apparatus for use in telemetry

An inspection apparatus for use in wellbores in the oil and gas industries relates in general to the field of transmission of data between downhole module in a wellbore and a controlling module at the surface. The invention provides a method and apparatus for determining analog filter parameters for an analog front end comprising a plurality of filter stages receiving signals from a telemetry module, by repeating the steps of; receiving a signal of a known frequency and processing said signal by determining the magnitude of the frequency of the received signal until a plurality of signals have been received and processed; calculating an optimum set of filter parameters in dependence upon the measured frequency magnitudes and a predefined set of filter stage frequency responses.

Steepest descent FFE computation and tracking
10129053 · 2018-11-13 · ·

A nonlinear equalizer for iteratively equalizing a data communication channel, which comprises a transmitter at the input of the channel, for transmitting data and one or more training sequences over the channel; a receiver at the output of the channel, for receiving the data and the one or more training sequences; a sampling circuit for sampling received data; a processor, for processing the samples. The processor is adapted to calculate the derivative of the MSE for each of the FFE taps; calculate the derivative of the variance of the enhanced noise with the FFE taps; iteratively update the FFE coefficients, while during each update, injecting samples of a known training sequence into the channel. During each update, the processor computes the derivative of the output noise variance, by applying convolution between the noise correlation and the current FFE taps; computes the effective channel and the modified effective channel; computes the derivative of the residual ISI, by applying correlation between the original channel h and the modified effective channel; and updates the FFE coefficients, with a step proportional to the opposite of the gradient.

VOLTAGE SAMPLER DRIVER WITH ENHANCED HIGH-FREQUENCY GAIN
20180302053 · 2018-10-18 ·

Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

Multilevel driver for high speed chip-to-chip communications
10091033 · 2018-10-02 · ·

Transmission line driver systems are described which are comprised of multiple paralleled driver elements. The paralleled structure allows efficient generation of multiple output signal levels with adjustable output amplitude, optionally including Finite Impulse Response signal shaping and skew pre-compensation.