A slicer circuit for use in a N-tap, S-bit symbol look-ahead decision feedback equalizer (DFE) wherein the slicer comprises overflow adders and sign adders, the slicer circuit including a first processing path for generating, based on a signal sample y(n), a most significant bit (MSB) for each of 2.sup.S*N possible output symbols of the DFE, the first processing path including (2.sup.S*N)/2 overflow adder circuits, and a second processing path for generating, based on the signal sample y(n), a least significant bit (LSB) for each of the 2.sup.S*N possible output symbols, the second processing path including 2.sup.S*N sign adder circuits.

A data slicer may include an input transistor configured to generate an internal output voltage based on an input voltage at an input node. An output node may be configured to output an output voltage based on the internal output voltage, and a feedback transistor may be configured to adjust the internal output voltage based on a correction voltage corresponding to output of the output node in a previous cycle.

A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

The present technology relates to a signal processing device, a signal processing method, and a program capable of reducing influence of crosstalk. Provided are: a plurality of comparators; a delay unit adapted to delay output of each of the plurality of comparators; and a subtractor adapted to subtract, from a supplied signal, a signal from the delay unit. The signal processing device processes signals transmitted in N phases and includes (N−1) or more comparators. Each of the plurality of comparators has a different threshold value set and compares a received signal with the threshold value, and in a case where the signal transitions between a plurality of voltage levels, the threshold value is set to a value within adjacent voltage levels. The present technology can be applied to a reception device that receives a signal transmitted in multiple phases and via multiple lines.

A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

In the present invention, a transmitting station apparatus includes a training signal generation unit, a transmission end linear equalization unit configured to output a plurality of second data signals obtained by equalizing IAI of a plurality of first data signals by using a transmission end transfer function for equalizing IAI, and a transmitting station communication unit configured to transmit a training signal or the plurality of second data signals to a receiving station apparatus and receive information on the transmission end transfer function from the receiving station apparatus, and the receiving station apparatus includes a communication path estimation unit configured to estimate a communication path response from the training signal received by the receiving station communication unit, a reception end coefficient calculation unit configured to calculate the transmission end transfer function and a reception end transfer function for equalizing ISI, based on the communication path response, and a reception end linear equalization unit configured to output a plurality of third data signals obtained by equalizing ISI from the plurality of second data signals received by the receiving station communication unit by using the reception end transfer function.

Embodiments include systems and methods for providing fast direct feedback to correct decision feedback equalization (DFE) in receiver circuits. Embodiments can provide direct feedback for DFE correction in a manner that is effective in high-speed data channels, while manifesting less latency, power consumption, and/or area than conventional DFE implementations. In some implementations, in each clock cycle (e.g., Tn), implementations can select (e.g., using a multiplexer) between a positive reference signal and a negative reference signal (e.g., both reference signals generated according to an inter-symbol interference magnitude for a data channel) according to a decision feedback signal from a previous clock cycle (Tn−1). The selected reference signal can be compared (e.g., in the same clock cycle Tn, using a comparator) with an input data signal to generated an updated decision feedback signal for a next clock cycle (e.g., Tn+1).

Circuits, devices, methods for decision feedback equalization are described. A decision feedback circuit can include L N-tap decision feedback equalizer (DFE) branch input lines and an unfolding multiplexer array network. The network is configured to generate at least one unfolded output based on inputs from a subset of the branch input lines and includes a plurality of multiplexer arrays wherein outputs from a first multiplexer array in the plurality of multiplexer arrays are connected to selection lines of a second multiplexer array in the plurality of multiplexer arrays.

Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

A decision feedback equalizer may include an input node, first and second paths, and a summation circuit. The input node may be configured to receive an input signal with an input symbol rate. The first and second paths may receive the input signal. The first path may include a first register configured to output a first signal based on the input signal such that the first signal has a sample symbol rate less than the input symbol rate. The second path may include a second register configured to output a second signal at the sample symbol rate based on the input signal. The summation circuit may be positioned between the input node and the first and second paths. The summation circuit may subtract the first and seconds signals at the sample symbol rate from the input signal before the input signal is provided to the first and second paths.