A channel equalization and tracking apparatus and method and a receiver. The apparatus includes: a Fourier transforming unit configured to transform a received time-domain signal into a frequency-domain signal; a compensating and equalizing unit configured to perform phase compensation and frequency-domain equalization on the signal outputted by the Fourier transforming unit by using one time of multiplication according to time delay information and an equalizer coefficient; a deciding unit configured to decide the equalized signal; and a channel tracking unit configured to track a channel according to the signal outputted by the Fourier transforming unit and an error signal obtained by the deciding unit. With embodiments of the present disclosure, not only complexity and hardware demands of the whole system are lowered, but also performance of the system is not affected.

Method and system for providing seamless match point switching in an adaptive decoder (e.g., an MLSE decoder) that is based on estimation of symbol sequences, according to which statistics regarding samples corresponding to different symbol sequences in alternative match points are collected by a statistics collector, to create a set of figures of merit representing the quality of each alternative match point, while different match points are obtained by changing the delay of symbols decoded by the adaptive decoder and samples entering the statistics collector. A figure of merit of the current match point is compared to the figure of merit of alternative match points. Whenever an alternative match point figure of merit is better than the current match point by a predefined threshold, a decision to switch to the alternative match point is made. Seamless switching to the alternative match point is performed by shifting the sampling phase forward or backward, until obtaining better performance, while performing adaptation of the decoder to the sampling phase shift.

Aspects of the disclosure relate to inter-link interference cancellation for reducing or mitigating interference from signals in different directions (e.g., uplink and downlink directions). A wireless communication device (i.e., a victim device subject to inter-link interference) may determine a time offset or lead time of an interfering signal from an offending device. Based on the determined time offset, the victim device may perform interference cancellation or suppression to reduce or mitigate the interference of the interfering signal. Other aspects, embodiments, and features are also claimed and described.

A system and method for measuring propagation delays and other delays in an optical switching system. A transmitter is connected, through a circuit switch, to a receiver. To measure the propagation delay between the transmitter and the receiver, the transmitter sends one or more time-tagged ranging messages and the receiver calculates a propagation delay from the difference between the time of receipt and the time of transmission. In another embodiment, a time delay between message transmission and transition of a CDR of the receiver to a fast acquisition mode is adjusted, by trial and error, to find a range of such time delays for which transmission is successful. A time delay between the transmitter and the switch is measured by establishing or breaking the connection and determining, for various tentative time delay values, whether transmission succeeds.

A post-equalization technique for recovering data bits from a coherent modulation optical signal is implemented in the digital domain by iteratively performing a decision-directed least mean square channel equalization step, a digital post filter step and a maximum likelihood sequence estimation step so that the symbol decisions of the previous iteration are fed to the decision directed least mean square channel equalization step to successively improve the symbol decisions. In an experimental setup, the iterative technique demonstrated performance improvement mitigating the bandwidth limitation as compared to a corresponding non-iterative technique.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A clock data recovery circuit includes; a clock recovery circuit that receives a pseudo random binary sequence (PRBS) pattern and generates a recovery clock by counting edges of the PRBS pattern, and a data recovery circuit that generates recovery data from at least one of the PRBS pattern and externally provided serial data.

A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.