Technology for performing multiple timing advances in a carrier aggregation communication system is disclosed. A method comprises communicating a random access preamble from a UE to an eNodeB via a PCell associated with a selected component carrier of the carrier aggregation. A Random Access Response (RAR) is received at the UE from the eNodeB for the PCell. The RAR contains a timing advance adjustment instructing the UE to adjust a timing of a PCell wireless communication. A request is received at the UE to adjust a timing of an SCell communication. A random access preamble is communicated to the UE via the SCell. An RAR is received at the UE from the eNodeB for the SCell to adjust a timing advance of the SCell wireless communication.

A method of interference cancellation is proposed. A UE obtains configuration information of a data transmission from a neighboring cell via an interference channel in a mobile communication network. The UE receives radio signals on a set of data resource elements as determined based on the obtained configuration information. The UE then estimates the interference channel corresponding to the data transmission from the neighboring cell based on the received radio signals on the set of data resource elements. Finally, the UE cancels the data transmission from the neighboring cell based on the estimated interference channel.

Briefly, in accordance with one or more embodiments, a fixed device synchronizes with a downlink channel of a network, acquires a master information block including a last system update time; and executes cell selection without acquiring other system information if the last system update time is before the last system access time. Furthermore, the fixed device may listen only for system information block messages that it needs, and ignore other system information blocks. A bitmap may indicate which system information block messages should be listed to for fixed devices, and which may be ignored. In some embodiments, one or more system information blocks may be designated for fixed devices.

A system for wired analog self-interference cancellation includes a coarse delayer that delays a sampled RF transmit signal by a first delay amount; a frequency downconverter that downconverts the sampled RF transmit signal to IF; a first canceller tap group comprising a first per-tap-group delayer, a first sampling coupler, a first per-tap delayer, and first and second analog vector modulators that generates an IF self-interference cancellation signal; a frequency upconverter that upconverts the IF self-interference cancellation signal to RF; and a receive coupler that combines the RF self-interference cancellation signal with the RF receive signal, reducing self-interference.

A method for adaptively-tuned digital self-interference cancellation includes generating a digital self-interference cancellation signal from a digital transmit signal based on a transform configuration; combining the digital self-interference cancellation signal with a receive signal to form a digital residue signal; generating a composite residue signal from the digital residue signal and the digital transmit signal; and updating the transform configuration based on the composite residue signal.

A system for wired analog self-interference cancellation includes a coarse delayer that delays a sampled RF transmit signal by a first delay amount; a frequency downconverter that downconverts the sampled RF transmit signal to IF; a first canceller tap group comprising a first per-tap-group delayer, a first sampling coupler, a first per-tap delayer, and first and second analog vector modulators that generates an IF self-interference cancellation signal; a frequency upconverter that upconverts the IF self-interference cancellation signal to RF; and a receive coupler that combines the RF self-interference cancellation signal with the RF receive signal, reducing self-interference.

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

An apparatus and a method. The apparatus includes a channel estimation (CE) module, including a first input for receiving pilot resource element (RE) observations, a second input for receiving data RE observations, a third input for receiving log-likelihood ratios (LLRs), and an output; a detector, including a first input connected to the output of the CE module, a second input for receiving data RE observations, and an output connected to the third input of the CE module; and a decoder, including an input connected to the third input of the CE module, and an output.

A method for performing self-interference cancellation by a communication device which uses an FDR mode can comprise the steps of: measuring the strength of a residual self-interference signal, after antenna and analog self-interference cancellation, for each subband with respect to a predetermined number of subbands configured in a communication device; determining the order of a nonlinear self-interference signal component, to be considered for channel estimation of a nonlinear self-interference signal, for each subband on the basis of the strength of the residual self-interference signal that has been measured for each subband; and performing channel estimation of the nonlinear self-interference signal on the basis of the order that has been determined for each subband.

A power amplifier cell includes a first input arranged to receive an in-phase control signal, a second input arranged to receive a quadrature control signal, an input stage arranged to output a drive signal based at least partly on the received in-phase and quadrature control signals, and an output stage arranged to receive at an input thereof the drive signal output by the input stage, and to generate an output signal for the power amplifier cell in response to the received drive signal.