Patent classifications
H04L25/03286
Methods and apparatus for decoding received uplink transmissions
Methods and apparatus for decoding received uplink transmissions. In an embodiment, a method includes receiving a stream having data LLRs and second channel state information (CSI2) LLRs, and separating the data LLRs into a data stream and the CSI2 LLRs into a CSI2 stream based on configuration parameters. The method also includes decoding the data stream to generate decoded data, and decoding the CSI2 stream to generate decoded CSI2 information. An apparatus includes a first LLR preprocessor that receives a stream having data LLRs and second channel state information (CSI2) LLRs and separates the data LLRs into a data stream, and a second LLR preprocessor that receives the stream and separates the CSI2 LLRs into a CSI2 stream. The apparatus also includes a data decoder that decodes the data stream to generate decoded data, and a CSI2 decoder that decodes the CSI2 stream to generate decoded CSI2 information.
ENCODED SIGNAL DEMODULATION METHOD, APPARATUS, DEVICE, AND COMPUTER READABLE STORAGE MEDIUM
The present disclosure relates to an encoded signal demodulation method, apparatus, and device. Some embodiments of the present disclosure are beneficial to improving demodulation performance.
Area efficient high-speed sequence generator and error checker
A combined error checker and sequence generator which shares a LFSR is disclosed which reduces complexity, cost, and area required for implementation while also improving timing margin. A clock and data recovery system recovers a data signal received over a channel from a remote transceiver. Control logic selects different modes of operation of the system. An error detector compares the two sequence signals and records errors in response to differences between the two sequence signals. A sequence generator generates a sequence signal for use by the error detector as a reference sequence signal or for transmission to a remote transceiver. The system includes one or more switching elements configured to selectively route the generated sequence as feedback into the sequence generator or the received sequence signal into the sequence generator subject to whether the combined error checker and sequence generator is in error checker mode or sequence generator mode.
Methods and apparatus for decoding received uplink transmissions
Methods and apparatus for decoding received uplink transmissions. In an embodiment, a method includes receiving a stream having data LLRs and second channel state information (CSI2) LLRs, and separating the data LLRs into a data stream and the CSI2 LLRs into a CSI2 stream based on configuration parameters. The method also includes decoding the data stream to generate decoded data, and decoding the CSI2 stream to generate decoded CSI2 information. An apparatus includes a first LLR preprocessor that receives a stream having data LLRs and second channel state information (CSI2) LLRs and separates the data LLRs into a data stream, and a second LLR preprocessor that receives the stream and separates the CSI2 LLRs into a CSI2 stream. The apparatus also includes a data decoder that decodes the data stream to generate decoded data, and a CSI2 decoder that decodes the CSI2 stream to generate decoded CSI2 information.
RECEIVER AND RECEIVE METHOD FOR A PASSIVE OPTICAL NETWORK
A receiver for a passive optical network is provided. The receiver includes an analog-to-digital converter circuitry configured generate a digital receive signal based on an analog receive signal. The analog receive signal is based on an optical receive signal encoded with a binary transmit sequence. The receiver additionally comprises linear equalizer circuitry configured to generate an equalized receive signal by linearly equalizing the digital receive signal. Further, the receiver comprises secondary equalizer circuitry configured to generate soft information indicating a respective reliability of elements in the equalized receive signal using the Viterbi algorithm. In addition, the receiver comprises decoder circuitry configured to generate a digital output signal based on the soft information using soft decision forward error correction.
END-TO-END CHANNEL ESTIMATION IN COMMUNICATION NETWORKS
A method for an end-to-end system for channel estimation includes obtaining data associated with a communication system. The communication system comprises a receiver, a transmitter, and a communication channel. A neural network is trained that models the communication channel of the communication system and this training is based on inputting the obtained data into the neural network and using a decoder. The neural network produces an output indicating a probability of a signal from the communication channel. The trained neural network is used for decoding information from the communication channel.
Bandwidth constrained communication systems with optimized low-density parity-check codes
In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.
METHODS AND APPARATUS FOR DECODING RECEIVED UPLINK TRANSMISSIONS
Methods and apparatus for decoding received uplink transmissions. In an embodiment, a method includes receiving a stream having data LLRs and second channel state information (CSI2) LLRs, and separating the data LLRs into a data stream and the CSI2 LLRs into a CSI2 stream based on configuration parameters. The method also includes decoding the data stream to generate decoded data, and decoding the CSI2 stream to generate decoded CSI2 information. An apparatus includes a first LLR preprocessor that receives a stream having data LLRs and second channel state information (CSI2) LLRs and separates the data LLRs into a data stream, and a second LLR preprocessor that receives the stream and separates the CSI2 LLRs into a CSI2 stream. The apparatus also includes a data decoder that decodes the data stream to generate decoded data, and a CSI2 decoder that decodes the CSI2 stream to generate decoded CSI2 information.
Systems and methods for phase noise mitigation in optical superchannels
A receiver architecture is described for phase noise compensation in the presence of inter-channel interference (ICI) and inter-symbol interference (ISI), particularly for time-frequency packing (TFP) transmissions. The receiver includes a coarse phase noise (PN) estimator, a PN compensation module, an ICI cancellation module, an ISI compensation module, a FEC decoder, and an iterative PN estimator. The iterative PN estimator receives log likelihood ratio (LLR) information from the decoder and provides an iterative PN estimation to the PN compensation module. The decoder also provides LLR to the ISI compensation module, and to at least one other receiver for another subchannel that is immediately adjacent in frequency. The ICI cancellation module receives decoder output from at least one adjacent subchannel, which the ICI cancellation module uses to provide a ICI-cancelled signal.
ADAPTIVE PAM4 DECISION FEEDBACK EQUALIZATION CIRCUIT
The present application relates to an adaptive PAM4 decision feedback equalization circuit, including a decision feedback equalization main circuit and an adaptive circuit. The main circuit includes an adder, a first decision device, a second decision device, a third decision device, a first delay unit group, a second delay unit group, a third delay unit group, a decoder, and a DSP coefficient table; the adaptive circuit includes an eye pattern monitoring module and an adaptive module; and the adaptive module includes a comparison unit, a delay unit, and a coefficient regulation and control unit.