An iterative two dimension equalizer usable in a receiver of orthogonal time frequency space (OTFS) modulated signals is described. In one configuration of the equalizer, a forward path generates, from received time-frequency domain samples and a channel estimate, estimates of data bits and likelihood numbers associated with the estimates of data bits, generated by delay-Doppler domain processing. In the feedback direction, the estimates of data bits are used to generate symbol estimates and autocorrelation matrix estimate in the time domain. In another configuration, a soft symbol mapper is used in the feedback direction for directly generating the feedback input symbol estimate without having to generate estimates of data bits.

A signal processing system and method, and an apparatus are provided. A phase recovery apparatus may be used to: receive a feedback signal fed back by an information iteration apparatus, perform, based on the feedback signal, phase recovery on a signal output by an equalizer, and output a phase-recovered signal to a post filtering apparatus, so that the post filtering apparatus performs noise filtering on the phase-recovered signal, and outputs a noise-filtered signal to the information iteration apparatus. To be specific, the phase recovery may be performed, based on the signal fed back by the information iteration apparatus, on the signal output by the equalizer. Because output of the information iteration apparatus is more accurate in determining the signal, precision of the phase recovery can be improved, cycle skipping is reduced, and input signal quality of the post filtering apparatus is improved.

The present disclosure provides for distortion cancelled by receiving a collided signal, the collided signal comprising a first signal carrying a first packet and a second signal carrying a second packet; amplifying and digitizing the collided signal into a first digital signal at a first gain and a second digital signal at a second gain that is greater than the first gain; determining a nonlinear interference component of the first packet on the second packet from the first digital signal; decoding the first packet from the first digital signal; re-encoding the first packet with a first estimated channel effect into an estimated signal; calculating a linear interference component of the first packet on the second packet from the estimated signal; removing the linear interference component and the nonlinear interference component from the second digital signal to produce a de-interfered signal; and decoding the second packet from the de-interfered signal.

Generating first and second discharge control signals in response to a clock signal and an input voltage signal, the first and second discharge control signals decreasing at different rates to a threshold level during a first time period, wherein a difference in rates is determined by the input voltage signal, generating a differential voltage on a pair of nodes during the first time period by selectively controlling a respective amount of discharge of an initial charge on each node of the pair of nodes by applying the first and second discharge control signals to respective transistors in a differential transistor pair connected to the pair of nodes, and maintaining the differential voltage on the pair of nodes during a subsequent time period, and generating an amplified differential voltage during at least a portion of the subsequent time period by amplifying the differential voltage.

In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.

The present application relates to an adaptive PAM4 decision feedback equalization circuit, including a decision feedback equalization main circuit and an adaptive circuit. The main circuit includes an adder, a first decision device, a second decision device, a third decision device, a first delay unit group, a second delay unit group, a third delay unit group, a decoder, and a DSP coefficient table; the adaptive circuit includes an eye pattern monitoring module and an adaptive module; and the adaptive module includes a comparison unit, a delay unit, and a coefficient regulation and control unit.

A wireless device includes first and second analog radio modules, first and second medium access control modules configured to control access to a digital network via the first and second analog radio modules, respectively, first and second baseband modules configured to convert between analog signals at the first and second analog radio modules, respectively, and digital signals at the first and second medium access control module, respectively, and circuitry configured to selectably coordinate the first and second medium access control modules to create a single-channel configuration for use by the wireless device to transmit and receive radio signals over a wireless interface, by setting the first and second analog radio modules to operate on a common frequency, and by commonly controlling the first and second baseband modules to convert common packets between analog and digital signals transmitted to or received from respective medium access control modules.

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

An iterative two dimension equalizer usable in a receiver of orthogonal time frequency space (OTFS) modulated signals is described. In one configuration of the equalizer, a forward path generates, from received time-frequency domain samples and a channel estimate, estimates of data bits and likelihood numbers associated with the estimates of data bits, generated by delay-Doppler domain processing. In the feedback direction, the estimates of data bits are used to generate symbol estimates and autocorrelation matrix estimate in the time domain. In another configuration, a soft symbol mapper is used in the feedback direction for directly generating the feedback input symbol estimate without having to generate estimates of data bits.

A communications apparatus to resolve a composite signal including an induced nonlinear distortion, a desired signal and interferer signals, wherein the desired signal includes desired symbols and the interferer signals include interferer symbols using N frameworks, each framework including a detector to partition the desired symbols and the interferer symbols based on an interference severity into a dominant group and a non-dominant group, and to generate A Posteriori Probabilities (APP) of the desired symbols and the interferer symbols, wherein the detector of each of the N frameworks generates the APP based on a feedback of the APP from each of the N frameworks, and the detector reduces the induced nonlinear distortion of the desired signal using a nonlinear mathematical model such as Volterra series.