Receivers using power saving and partial decision feedback equalization (DFE) methods are provided. A receiver includes a slicer circuit configured to allow multiple comparator circuits to output multiple decision values, the multiple comparator circuits being connected to a data line and configured to compare a data symbol with multiple reference voltage levels, respectively, in response to multiple clock signals, respectively, a decoder configured to decode the data symbol, based on the multiple decision values, and a control circuit connected to the slicer circuit and configured to store the multiple decision values as a previous data symbol value and, based on the previous data symbol value, selectively provide the multiple clock signals to the slicer circuit. When the previous data symbol value corresponds to the lowest level, the control circuit disables a first comparator circuit to decide the highest level, from among the multiple comparator circuits.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may generate a pre-equalized waveform associated with a multiple-input multiple-output (MIMO) communication system. The wireless communication device may transmit the pre-equalized waveform using a per-MIMO-layer transport block (TB). Numerous other aspects are described.

A host and one or more devices can communicate with each other using signals that couple communication data with power. The host can transmit the coupled data and the other device can decouple the communication data from the power. Further, the receiving device can replicate the transmitted communication signal without digital signal processing. The host and the devices can communicate with each other using a data frame in which one of the devices initially generates a first portion of the data frame and transmits the first portion, and the other device subsequently generates and transmits a second portion of the data frame. The data frame may include one or more frame sync data used to calibrate and align clock signals from clock circuits. Systems and methods for identifying data when a system is unaware of the protocol are also shown.