A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

The present disclosure relates to systems and methods for transmitting data in a video signal. The systems may perform the methods to generate a data frame, wherein the data frame may include at least a frame header and frame data, the frame header may include at least one autocorrelation and cross-correlation sequence; insert the data frame into an area of a video signal, wherein the inserted area of the video signal is not an area of line and field synchronization or an area of effective video; transmit the video signal having the data frame to another device.

A wireless communication method for transmitting wireless signals from a transmitter includes receiving information bits for transmission, segmenting the information bits into a stream of segments, applying a corresponding forward error correction (FEC) code and an interleaver to each of the stream of segments and combining outputs of the interleaving to generate a stream of symbols, processing the stream of symbols to generate a waveform, and transmitting the waveform over a communication medium.

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.