.[.An equal gain composite beamforming technique which includes the constraint that the power of the signal output by each antenna is the same, and is equal to the total power of the transmit signal divided by the number N of transmit antennas from which the signal is to be transmitted. By reducing output power requirements for each power amplifier, the silicon area of the power amplifiers are reduced by as much as N times (where N is equal to the number of transmit antennas) relative to a non-equal gain composite beamforming technique..]. .Iadd.A method and apparatus are disclosed for a multiple input multiple output (MIMO) transmission technique by a wireless communications device which includes providing that the power applied to each transmit antenna may be equal to the total power of the transmit signal divided by the number N of transmit antennas from which the signal is to be transmitted. The device may produce a weight for each of the N transmit antennas used in MIMO transmission. Also, the device may determine a total transmit power and produce a multi-carrier signal for transmission. The device may weight the multi-carrier signal for each antenna per the produced weight. Further, the device may apply a power to each of the N transmit antennas, for the weighted multicarrier signal, which is equal to the total transmit power divided by N. Each transmit antenna signal may be amplified by an amplifier coupled to that antenna..Iaddend.

Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

A transceiver and a corresponding method configured to recover within less than 1 ms from quality degradation in its operating point. The transceiver includes: a receiver analog front end (Rx AFE), an adaptive module comprising at least one of an adaptive digital equalizer and an adaptive digital canceller (ADEC), a common mode sensor AFE (CMS-AFE), a fast-adaptive mode-conversion canceller (FA-MCC), and a slicer. The Rx AFE receives signals from a second transceiver. Shortly after identifying quality degradation in the transceiver's operating point, the transceiver indicates the second transceiver to reduce the rate of the transmitted data. And within less than 1 ms, the transceiver utilizes the improved detection rate to improve the accuracy of the slicing errors, which enables fast adaptation of the ADEC, that improves the quality in the transceiver's operating point to a level that enables the transceiver to indicate the second transceiver to increase the rate.

An optical communication system, a circuit, and a method of operating an optical communication system are provided. The optical communication system is disclosed to include a photodiode configured to receive optical signals and convert the received optical signals into electrical signals, a Trans-Impedance Amplifier (TIA) electrically connected with the photodiode such that the TIA receives the electrical signals from the photodiode and is configured to convert the electrical signals received from the photodiode into amplified electrical signals, and a feedback loop connected between an input of the TIA and an output of the TIA that includes a switchable capacitor bank connected thereto which introduces at least one zero into a feedback factor transfer function of the TIA thereby tuning out poles or equalizing delay introduced by a TIA input network connected between the photodiode and the input of the TIA.

An integrated circuit may include receiver circuitry that receives data from an external device. Such receiver circuitry may include, among other things, equalization circuitry that may reconstruct the received data before transmitting the received data to other parts of the integrated circuit. The receiver circuitry may include two different equalization circuits. A first equalization circuit may perform equalization on the received data to generate a first equalized output while a second equalization circuit may generate a second equalized output. The receiver circuitry may further include an amplifier circuit that selectively amplifies either the first or second equalized output from the respective first and second equalization circuits based on the data rate of the received data.

An equalization signal processing circuit includes: a signal division unit that divides an input signal of oversampling of a rational number M/L multiple into M signals; a first frequency domain filter that performs an arithmetic operation of a first filter coefficient on M signals in a frequency domain; a second frequency domain filter that performs an arithmetic operation of a second filter coefficient on, for each L group, M signals on which the arithmetic operation of the first filter coefficient is performed; a time domain conversion unit that converts a signal added for each group into a signal in a time domain; a switch circuit that sequentially selects a signal converted into a signal in the time domain for each group; and a coefficient updating unit that updates the first filter coefficient and the second filter coefficient.