A receiver is configured to capture a plurality of linearly distorted OFDM symbols transmitted over a signal path. The receiver forms the captured OFDM symbols into an overlapped compound data block that includes payload data and at least one pseudo-extension, processes the overlapped compound block with circular convolution in the time domain using an inverse channel response, or frequency domain equalization, to produce an equalized compound block, and discards end portions of the equalized block to produce a narrow equalized block. The end portion corresponds with the pseudo-extension, and the narrow block corresponds with the payload data. The receiver cascades multiple narrow equalized blocks to form a de-ghosted signal stream of OFDM symbols. The OFDM symbols may be OFDM or OFDMA, and may or may not include a cyclic prefix, which will have a different length from the pseudo-extension.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

A multi building block architecture may be configured to generate a waveform (a target wideband signal) for use in a wireless communication system, where the waveform supports a variety of baseband signals. The task of generating a target wideband signal can be divided into several tasks, each task relating to the generating of one of a plurality of sub-carrier bands. Each of the sub-carrier bands (sub-bands) may be generated by one of the sub-band building units included in the sub-band building blocks of the architecture. Several sub-bands may be formed, by a sub-band group building block, into a sub-band group. Multiple sub-band groups may be formed, by a wideband building block, into the target wideband signal.

A receiver is configured to capture a plurality of linearly distorted OFDM symbols transmitted over a signal path. The receiver forms the captured OFDM symbols into an overlapped compound data block that includes payload data and at least one pseudo-extension, processes the overlapped compound block with circular convolution in the time domain using an inverse channel response, or frequency domain equalization, to produce an equalized compound block, and discards end portions of the equalized block to produce a narrow equalized block. The end portion corresponds with the pseudo-extension, and the narrow block corresponds with the payload data. The receiver cascades multiple narrow equalized blocks to form a de-ghosted signal stream of OFDM symbols. The OFDM symbols may be OFDM or OFDMA, and may or may not include a cyclic prefix, which will have a different length from the pseudo-extension.

An apparatus includes an optical receiver that includes a processor. The receiver is configured to direct a digital-electrical representation of a received symbol value of a pulse-amplitude modulated signal to a frequency-domain processing path of the processor and to a time-domain processing path of the processor. The processor is configured to compute, in the frequency-domain processing path, a first product of the received symbol value and a first coefficient, and to compute a second product of the received symbol value and a second coefficient. The processor is further configured to compute, in the time-domain processing path, an estimated error metric based on the first and second products, and to determine an updated first coefficient and an updated second coefficient based on said error metric. The processor is further configured to equalize a subsequent received symbol using the updated coefficients.