A method of correcting an error in an IQ signal generator system includes: generating, by a baseband circuit, a baseband IQ signal having a baseband I signal part and a baseband Q signal part; modulating, by an IQ modulator circuit, the baseband IQ signal, thereby obtaining a modulated IQ signal; determining, by an analysis circuit, a level curve of the modulated IQ signal, wherein the level curve is associated with a signal level of the modulated IQ signal over time; determining, by the analysis circuit, at least one error quantity based on the level curve, wherein the level curve multiplied with a spectral factor is integrated in order to determine the at least one error quantity; and controlling, by a control circuit, the baseband circuit or the IQ modulator circuit based on the at least one error quantity determined, thereby correcting an error in the IQ signal generator system.

Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for optimization of mapping and demapping for wireless communication channels. In some implementations, a transmitter includes a mapper that has been trained through machine learning training. The transmitter is trained based at least in part on demapper characteristics for a demapper of a receiver. The mapper has parameter values that have been trained to at least partially compensate for non-linear distortion of signals in a wireless communication channel, including through application of non-linear distortion during training. The mapper is configured to map data to be transmitted to symbols in a symbol constellation for transmission. The parameter values of the mapper define characteristics of the symbol constellation including amplitude or phase of the symbols in the symbol constellation.

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

A processor can be configured to execute instructions stored in the memory to position a first point in a grid space that represents an unmodulated signal component of a first signal based on a characteristic of a frequency modulator generating the first signal. The frequency modulator can include a first input to receive data from a baseband source and can include a second input to receive a second signal from a local oscillator. The processor can determine, in the grid space, a first angle between a first line segment from a reference point to the first point and a second line segment from the first point to a point representing the first offset signal applied to the frequency modulator. The processor can additionally apply a second offset signal, based on the first angle, to compensate for the characteristic of the frequency modulator.

Systems and devices are provided for receiving or transmitting IQ data (e.g., suitable for passband quadrature amplitude modulation (QAM)) over a wireline using pairs of baseband pulse amplitude modulation (PAM-n) signals. Encoding circuitry may map data from an input bit stream to IQ data that includes an in-phase component and a quadrature-phase component. Modulator circuitry may determine an in-phase PAM-n signal based on the in-phase component and a quadrature-phase PAM-n signal based on the quadrature-phase component. Driver circuitry may transmit the in-phase PAM-n signal and the quadrature-phase PAM-n signal across a wireline channel. The in-phase PAM-n signal may be different by 90 from the quadrature-phase PAM-n signal. This may enable a remote receiver on the wireline channel to detect the in-phase PAM-n signal independently of the quadrature-phase PAM-n signal.

Embodiments herein disclose a phase control circuit for a high-speed ADC clock receiver in a PAM4 receiver comprises of, a plurality of Current-Mode Logic (CML) IQ dividers, a plurality of phase interpolators, and a detector circuit, wherein the detector circuit determines phase relation between plurality of clock signals from the plurality of CML IQ dividers and control inputs of the plurality of phase interpolators in a clock data recovery loop based on the determined phase relation.

A digital to analog signal conversion system with a local oscillator, a control circuit, a radio-frequency digital to analog converter circuit, and a power combiner circuit is presented. The local oscillator generates a plurality of local oscillator phase signals. The control circuit receives a baseband in-phase (I) signal and a baseband quadrature (Q) signal and generates a plurality of control signals. The radio-frequency digital to analog converter circuit includes first and second pluralities of switch units that generate positive and negative radio-frequency signals respectively, based on the plurality of local oscillator phase signals and the plurality of control signals. The power combiner circuit generates a radio-frequency output signal based on a combination of the positive radio-frequency signal from the first plurality of switch units and the negative radio-frequency signal from the second plurality of switch units.