Disclosed herein is a broadcast signal transmitter. The broadcast signal transmitter according to an embodiment of the present invention includes an input formatting module configured to perform baseband formatting and to output at least one Physical Layer Pipe (PLP) data, a BICM module configured to perform error-correction processing on the PLP data, a framing and interleaving module configured to interleave the PLP data and to generate a signal frame, and a waveform generation module configured to insert a preamble into the signal frame and to generate a broadcast signal by OFDM-modulate the signal frame.

Described is a method of searching of multichannel signal and technique of demodulating and detecting DBPSK frequency division multiple access (FDMA) ultra-narrow band signal. A search is based on algorithm encompassing a signal-processing signal, and technique to demodulate and detect FDMA ultra-narrow band together with a method to increase time-frequency resolution.

One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, a receiver has a receiver front end configured to receive time domain data in natural order, a fast Fourier transform module configured to generate frequency domain data in digit reversed order based on the time domain data, a demodulator configured to generate first demodulated data in digit reversed order based on the frequency domain data, and a de-interleaver configured to perform a reordering permutation on the first demodulated data to generate second demodulated data in natural order.

A method performed in a radio access node includes the radio access node receiving a data for transmission to a second radio access node over a communication channel having an unlicensed spectrum. The method further includes, in response to receiving the data, the radio access node receiving a channel measurement signal over the communication channel. The method further includes the radio access node performing an N-point Fast Fourier Transform (FFT) on the channel measurement signal to produce a frequency domain signal with N bins. The method further includes the radio access node performing a power measurement on the frequency domain signal. The method further includes the radio access node analyzing the power measurement of the frequency domain signal. The method further includes the radio access node transmitting the data based on the analysis of the power measurement.

Methods and OFDM receivers for decoding an OFDM signal include estimating a channel impulse response from a pilot-dense symbol of the OFDM signal for each of a plurality of potential FFT window positions; determining a noise floor of each of the channel impulse responses; selecting the potential window position corresponding to the channel impulse response with the lowest noise floor as an optimum FFT window position; and decoding symbols of the OFDM signal using the optimum FFT window position.

A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.

The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.

An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.

An embedded system is described. The embedded system includes a processing circuit comprising at least one processor configured to support an implementation of a non-power-of-2 fast Fourier transform of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers; and a memory, operably coupled to the processing circuit and comprising at least input data. The processing circuit is configured to: receive an input data complex number sequence; adapt the input data complex number sequence by inserting at least one zero into every X.sup.th data point that results in an excess number of data points above N, where X=N1, such that the inserted zeroes enables a use of a multiple-of-Q FFT; perform a first decomposed FFT of a respective first length N1 on the adapted input data complex number sequence and produce a first output complex number sequence; restore a number of data points of the first output complex number sequence to N after performing the first decomposed FFT; and perform a second decomposed FFT of a respective second length N2 on the first output complex number sequence that produces a second output complex number sequence.

An embedded system is described. The embedded system includes a processing circuit comprising a processing circuit comprising Q processing units that can be operated in parallel. The processing circuit is configured to support an implementation of a non-power-of-2 fast Fourier transform of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers. A memory is operably coupled to the processing circuit and includes at least input data. The processing circuit is configured to: employ a customized instruction configured to perform an FFT operation of length less than Q using a first of the at least two smaller FFTs.