The present disclosure generally relates to a shielded three-layer patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. To reduce costs, PCBs are being made with only four total layers separated by dielectric material. Conductive traces in PCBs can have the problem of common mode current flowing through the traces and thus increasing the magnitude of EMI noise. By providing a shielded three-layer patterned ground structure, not only is the cost reduced, but so is the common mode current and the magnitude of EMI noise, all without any negative impact to the differential signal.

Systems and methods for a flexible dynamic loop having reduced impedance are described. The flexible dynamic loop may supply current from a preamplifier to another device, such as a hard disk drive. In one embodiment, a flexible dynamic loop comprises a flexible structure having a set of wire traces. The flexible dynamic loop may also comprise a set of impedance control structures on the flexible structure and perpendicular to a bend radius of the flexible structure, wherein the set of impedance control structures change an impedance level experienced by at least some of the set of wire traces. Some of the impedance control structures may be staggered. The flexible dynamic loop may also include a cover layer formed over the set of impedance control structures, which may be patterned with perforations. The flexible dynamic loop may also include one or more flexible rails connecting some of the impedance control structures.

Certain aspects of the present disclosure relate to methods and apparatus for allocating resources for the transmission of scheduling requests based on UE traffic profiles. In one embodiment, a base station determines, for one or more user equipments (UEs), a type of traffic to be exchanged between the one or more UEs and the base station. The base station allocates resources for the one or more UEs to use for sending a scheduling request based, at least in part, on the type of traffic associated with each of the one or more UEs. The base station signals an indication of the allocated resources to each of the one or more UEs.

Disclosed is a printed circuit board. The printed circuit board includes an insulating layer, a copper foil formed on the insulating layer and formed therein with a groove to expose a portion of a top surface of the insulating layer, and a thermal conductive layer filled in the groove.

Systems for shielding bent signal lines provide ways to couple different antenna arrays for radio frequency (RF) integrated circuits (ICs) (RFICs) associated therewith where the antenna arrays are oriented in different directions. Because the antenna arrays are oriented in different directions, the antenna structures containing the antennas may be arranged in different planes, and signal lines extending therebetween may include a bend. To prevent electromagnetic interference (EMI) or electromagnetic crosstalk (EMC) from negatively impacting signals on the signal lines, the signal lines may be shielded. The shields may further include vias connecting the mesh ground planes and positioned exteriorly of the signal lines. The density of the vias may be varied to provide a desired rigidity in planes containing the antenna arrays while providing a desired flexibility at a desired bending location in the signal lines to help bending process accuracy.

Apparatus and methods are provided for providing provide high-speed traces in inner layers of semiconductor packages or PCBs. In an exemplary embodiment, there is provided an circuit assembly that may comprise a first ground reference plane, a second ground reference plane and a dielectric layer between the first ground reference plane and the second ground reference plane. The dielectric layer may comprise a pair of traces embedded therein and the first ground reference plane may have an opening corresponding to the pair of traces. The opening may have a width equal to or larger than a width of the pair of traces, which may be equal to widths of respective traces of the pair of traces and a gap between the pair of traces.

A printed circuit board, includes: a first insulating layer on which a wiring line is disposed; a second insulating layer covering an upper portion of the wiring line; a first conductive shield wall spaced apart from two opposing sides of the wiring line in a width direction of the wiring line, and extending in a length direction of the wiring line; and a second conductive shield wall spaced apart from two opposing ends of the first conductive shield wall in the length direction, and extending the a width direction. At least one of the first conductive shield wall or the second conductive shield wall includes a plurality of via walls each extending in a thickness direction of the first insulating layer and the second insulating layer and having a gap is disposed therebetween.

A printed circuit board (PCB) includes a substrate defining a major plane. A first side of the major plane is configured for mounting of functional circuit elements. A cable connector is mounted on a second side of the major plane of the substrate, opposite the first side, for coupling to a shielded radiofrequency (RF) communications cable. At least one component grounding layer is parallel to the major plane and configured for coupling to the functional elements. At least one cable grounding layer is parallel to the major plane and is separated from the at least one component grounding layer. Each cable grounding layer in the at least one cable grounding layer is coextensive with the substrate and is configured for coupling, through the connector, to shielding of the shielded RF communications cable, without coupling to any other component. Nodes of an RF communications system may be mounted on such PCBs.

Embodiments described herein are directed to methods and apparatus for power distribution. The apparatus can include a power distribution network for a plurality of integrated circuits (IC). According to embodiments, the power distribution network includes a plurality of overlapping power/ground (PG) plane segments and one or more non-overlapping PG (no-PG) plane segments. Each overlapping-PG plane segment is separated from another overlapping-PG plane segment by at least one no-PG plane segment. The no-PG plane segments can include at least one of a multilayered power (P) plane segment with no ground reference of any PG plane and a multilayered ground (G) plane segment with no power reference of any PG plane.

In accordance with at least one aspect of this disclosure, a system can include, a printed circuit board (PCB), a controller on the PCB configured to output a gate drive signal to one or more gate drivers 106 to drive a gate 108 of a switch (e.g., a transistor), and an isolation domain. The isolation domain can be defined in the PCB between the controller and the one or more gate drivers. More specifically, the isolation domain can begin at a first moat and end at a second moat, defined between the controller and the one or more gate drivers. The isolation domain can be configured to prevent common mode noise in the gate drive signal.