Selective deposition methods are described. An exemplary method comprises exposing the substrate comprising a first surface and a second surface to an anchor reactant and selectively depositing the anchor reactant on the first surface as a seed layer, wherein the anchor reactant comprises an ethynyl derivative with a headgroup that selectively targets the first surface.

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

Provided are an active matrix substrate having a reduced driving voltage and excellent adhesion between a dielectric layer and a water-repellent layer and a microfluidic device including the substrate. The active matrix substrate includes an array electrode, a dielectric layer covering the array electrode, and a first water-repellent layer in this order on a first substrate. The dielectric layer includes a silicon nitride film located on the side in contact with the first water-repellent layer, and the silicon nitride film has a surface layer region containing oxygen in the surface on the side in contact with the first water-repellent layer.

A method of etching a substrate including an etching film and a mask formed on the etching film is provided. The mask includes a first pattern of a first recess having a first opening and a second pattern of a second recess having a second opening. The method includes etching the etching film to a predetermined depth; depositing a protective film on the mask after the etching; and etching the etching film after the depositing. The first opening is smaller than the second opening. As a result of the depositing, the first opening of the first pattern is clogged and the second opening of the second pattern is not clogged.

A method for producing an organic electronic component and an organic electronic component are disclosed. In an embodiment the component comprises at least one organic electronic layer having a matrix, wherein the matrix contains a metal complex as a dopant, wherein the metal complex comprises at least one metal atom M and at least one ligand L bonded to the metal atom M.

A method for separating semiconductor dies of a semiconductor die assembly comprises depositing a first coating on a first surface of the assembly. The assembly comprises a die wafer having a plurality of semiconductor dies and first and second surfaces. A first portion of the die wafer and the first coating is removed between adjacent semiconductor dies to form trenches having an intermediate depth in the die wafer between first and second surfaces such that die corners are formed on either side of the trenches. A protective coating is deposited on the first surface of the die assembly to cover the die corners, trenches and at least a portion of the first coating. The first coating is selectively removed such that portions of the protective coating covering die corners and trenches remain on the die wafer. Adjacent semiconductor dies are separated and the protective coating remains covering the die corners.

A method for forming multi-layer film on substrate, which includes steps (1) forming under layer film on substrate by applying under layer film material containing resin having repeating unit represented by the general formula (1) or (2) in which fluorene structure is contained, and curing the same by heat treatment, (2) forming metal oxide film on the under layer film by applying metal oxide film material selected from titanium oxide film material, zirconium oxide film material, and hafnium oxide film material, (3) forming hydrocarbon film on metal oxide film by applying hydrocarbon film material, and (4) forming silicon oxide film on the hydrocarbon film by applying silicon oxide film material. There can be provided a method for forming multi-layer film that can reduce reflectance, and useful for a patterning process with high dimensional accuracy of dry etching. ##STR00001##

The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.

A method for etching a target layer on a substrate by a dry etching process includes at least one etching cycle, wherein an etching cycle includes: depositing a halogen-containing film using reactive species on the target layer on the substrate; and etching the halogen-containing film using a plasma of a non-halogen etching gas, which plasma alone does not substantially etch the target layer, to generate etchant species at a boundary region of the halogen-containing film and the target layer, thereby etching a portion of the target layer in the boundary region.

Facilitating throughput in nanoimprint lithography processes by using an imprint resist including fluorinated components and a substrate treated with a pretreatment composition to promote spreading of an imprint resist on the substrate. The interfacial surface energy between the pretreatment composition and air exceeds the interfacial surface energy between the imprint resist and air by at least 1 mN/m, and the contact angle of the imprint resist on the surface of the nanoimprint lithography template is less than 15°.