Methods for seam-less gapfill comprising forming a flowable film by exposing a substrate surface to a silicon-containing precursor and a co-reactant are described. The silicon-containing precursor has at least one akenyl or alkynyl group. The flowable film can be cured by any suitable curing process to form a seam-less gapfill.

There is provided a technique that includes forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a precursor gas to the substrate in a process container of a substrate processing apparatus via a first pipe made of metal; (b) supplying an oxygen-containing gas to the substrate in the process container via a second pipe made of metal, wherein a fluorine-containing layer is continuously formed on an inner surface of the second pipe; and (c) supplying a nitrogen-and-hydrogen-containing gas to the substrate in the process container via the second pipe.

There is provided a technique that includes (a) forming a first film having a first thickness on an underlayer by supplying a first process gas not including oxidizing gas to a substrate, wherein the first film contains silicon, carbon, and nitrogen and does not contain oxygen, and the underlayer is exposed on a surface of the substrate and is at least one selected from the group of a conductive metal-element-containing film and a nitride film; and (b) forming a second film having a second thickness larger than the first thickness on the first film by supplying a second process gas including oxidizing gas to the substrate, wherein the second film contains silicon, oxygen, and nitrogen, and wherein in (b), oxygen atoms derived from the oxidizing gas and diffuse from a surface of the first film toward the underlayer are absorbed by the first film and the first film is modified.

Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

Processing methods disclosed herein comprise forming a nucleation layer and a flowable chemical vapor deposition (FCVD) film on a substrate surface by exposing the substrate surface to a silicon-containing precursor and a reactant. By controlling at least one of a precursor/reactant pressure ratio, a precursor/reactant flow ratio and substrate temperature formation of miniature defects is minimized. Controlling at least one of the process parameters may reduce the number of miniature defects. The FCVD film can be cured by any suitable curing process to form a smooth FCVD film.

In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

There is provided a technique that includes (a) supplying a fluorine-containing gas to a substrate including a first surface and a second surface; (b) supplying an oxygen- and hydrogen-containing gas and a catalyst to the substrate after performing (a); (c) supplying a modifying agent to the substrate after performing (b); and (d) supplying a film-forming agent to the substrate after performing (c).

Methods of forming patterned features and structures including the patterned features are disclosed. Exemplary methods include selectively forming a surface energy modified surface on a sidewall of structures and/or forming a surface-energy tunable layer on a surface of the substrate. The surface energy modified surface can be formed by depositing material and/or by treating the sidewall surface and/or by treating a surface adjacent the sidewall surface.