Semiconductor devices and methods of manufacturing are presented in which a first spacer layer and a second spacer layer are formed. In embodiments the first spacer layer and the second spacer layer are formed with an enhanced etch resistance. Such an enhanced etch resistance works to help prevent undesired breakthroughs during subsequent manufacturing processes.

Methods for depositing SiOC and SiOCN films are disclosed. Exemplary methods utilize precursors containing iodine and alkoxide, and can be used to form low-k spacers using O-free PEALD.

A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

A method for manufacturing a semiconductor device having a low-k carbon-containing dielectric layer includes: depositing a low-k carbon-containing dielectric material, which has a carbon content ranging from 16 atomic % to 23 atomic %, using a precursor mixture to form a carbon-containing dielectric layer having a k value ranging from 2.8 to 3.3 and a porosity ranging from 0.03% to 1.0%; forming the carbon-containing dielectric layer into a patterned carbon-containing dielectric layer having a recess therein by etching, the patterned carbon-containing dielectric layer having a porosity ranging from 1.0% to 2.0%; and filling the recess with an electrically conductive material to form an electrically conductive feature in the patterned carbon-containing dielectric layer.

The technology of this application relates to a switching power module that includes a substrate, a die embedded in the substrate, and a packaging layer. The packaging layer covers an integrated circuit layout layer of the die. The packaging layer packages the integrated circuit layout layer of the die, the die includes a composite material layer covering the integrated circuit layout layer, and the composite material layer includes at least two material layers that have different functions. The at least two material layers include a first material layer covering the integrated circuit layout layer, the first material layer is a mixed layer of undoped silicate glass and tetraethyl orthosilicate, and the first material layer is filled in a gap between metal protrusions of the integrated circuit layout layer, thereby improving an isolation effect between the metal protrusions. The mixed layer of the undoped silicate glass and the tetraethyl orthosilicate has a good thermal stress effect.

Provided are a graphene interconnect structure, an electronic device including the graphene interconnect structure, and a method of manufacturing the graphene interconnect structure. The graphene interconnect structure may include: a first oxide dielectric material layer; a second oxide dielectric material layer on a surface of the first oxide dielectric material layer and having a dielectric constant greater than that of the first oxide dielectric material layer; and a graphene layer on a surface of the second oxide dielectric material layer opposite to the surface on which the first oxide dielectric material layer is located.

A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

There is provided a technique that includes: (a) forming a film formation suppression layer on a surface of a first material of a concave portion of the substrate, by supplying a precursor to the substrate provided with the concave portion on a surface of the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion having a top surface and a side surface composed of the first material containing a first element and a bottom surface composed of a second material containing a second element; and (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the film formation suppression layer formed on the surface of the first material.

Provided is a photosensitive resin composition that includes: a silicone resin (A) having an epoxy group and/or a phenolic hydroxyl group; an alkyl phenol novolac resin (B) indicated by formula (B); and a photoacid generator (C).

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(In the formula, R.sup.51 is a C1-9 saturated hydrocarbyl group. R.sup.52 is a C10-25 saturated hydrocarbyl group. n.sup.1 and n.sup.2 are numbers that fulfil 0≤n.sup.1<1, 0<n.sup.2≤1, and n.sup.1+n.sup.2=1. m.sup.1 represents an integer from 0 to 3 and m.sup.2 represents an integer from 1 to 3.)