Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.

A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.

Provided is a composition for forming a film for semiconductor devices, including: a compound (A) including a SiO bond and a cationic functional group containing at least one of a primary nitrogen atom or a secondary nitrogen atom; a crosslinking agent (B) which includes three or more C(?O)OX groups (X is a hydrogen atom or an alkyl group having from 1 to 6 carbon atoms) in the molecule, in which from one to six of three or more C(?O)OX groups are C(?O)OH groups, and which has a weight average molecular weight of from 200 to 600; and a polar solvent (D).

A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

A device includes a semiconductor substrate, a gate stack, and an interlayer dielectric. The gate stack is over the semiconductor substrate. The interlayer dielectric is over the semiconductor substrate and surrounds the gate stack. The interlayer dielectric includes a liner layer and a filling layer. The liner layer lines the gate stack. The filling layer is over the liner layer and includes a metal-contained ternary dielectric material.

Methods for depositing a metal containing material formed on a certain material of a substrate using an atomic layer deposition process for semiconductor applications are provided. In one embodiment, a method of forming a metal containing material on a substrate comprises pulsing a first gas precursor comprising a metal containing precursor to a surface of a substrate, pulsing a second gas precursor comprising a silicon containing precursor to the surface of the substrate, forming a metal containing material selectively on a first material of the substrate, and thermal annealing the metal containing material formed on the substrate.

In a method of deposition a thin film, a substrate having a pattern may be provided. A surface of the substrate may be treated using a deposition-suppressing gas to form a deposition-suppressing layer on the pattern. A process gas may be applied to the pattern to deposit the thin film. The deposition-suppressing gas may include fluorine.

A field-effect transistor includes a gate electrode, a source electrode and a drain electrode to take out electric current according to an application of a voltage to the gate electrode, a semiconductor layer disposed adjacent to the source electrode and the drain electrode, the semiconductor layer forming a channel between the source electrode and the drain electrode, a first insulating layer as gate insulating film disposed between the semiconductor layer and the gate electrode, and a second insulating layer covering at least a part of a surface of the semiconductor layer, the second insulating layer including an oxide including silicon and alkaline earth metal.

Disclosed is a display apparatus including a substrate; an insulating layer disposed on the substrate; a wiring layer disposed on the insulating layer; and a side surface protective layer disposed on a side surface of the wiring layer and having an electrical insulation property, wherein the wiring layer has a stack structure in which a plurality of layers are stacked. In this regard, the side surface protective layer covers a side surface of each of at least some of the plurality of layers of the stack structure.

A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.