Disclosed are methods of depositing films of material on multiple semiconductor substrates in a multi-station processing chamber. The methods may include loading a first set of one or more substrates into the processing chamber at a first set of one or more process stations and depositing film material onto the first set of substrates by performing N cycles of film deposition. Thereafter, the methods may further include transferring the first set of substrates from the first set of process stations to a second set of one or more process stations, loading a second set of one or more substrates at the first set of process stations, and depositing film material onto the first and second sets of substrates by performing N′ cycles of film deposition, wherein N′ is not equal to N. Also disclosed are apparatuses and computer-readable media which may be used to perform similar operations.

A processing chamber such as a plasma etch chamber can perform deposition and etch operations, where byproducts of the deposition and etch operations can build up in a vacuum pump system fluidly coupled to the processing chamber. A vacuum pump system may have multiple roughing pumps so that etch gases can be diverted a roughing pump and deposition precursors can be diverted to another roughing pump. A divert line may route unused deposition precursors through a separate roughing pump. Deposition byproducts can be prevented from forming by incorporating one or more gas ejectors or venturi pumps at an outlet of a primary pump in a vacuum pump system. Cleaning operations, such as waferless automated cleaning operations, using certain clean chemistries may remove deposition byproducts before or after etch operations.

A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

A semiconductor processing system processes semiconductor wafers in a process chamber. The process chamber includes semiconductor process equipment for performing semiconductor processes within the chamber. The process chamber includes a heat pipe integrated with one or more components of the process chamber. The heat pipe effectively transfers heat from within the chamber to an exterior of the chamber.

A method for forming a semiconductor structure comprising a silicon-on-insulator layer structure with crystalline silicon oxide SiO.sub.x as the insulator material comprises: providing a crystalline silicon substrate having a substantially clean deposition surface in a vacuum chamber; heating the silicon substrate to an oxidation temperature To in the range of 550 to 1200 ° C.; supplying, while keeping the silicon substrate in the oxidation temperature, with an oxidation pressure P.sub.o in the range of 1.Math.10.sup.−8 to 1.Math.10.sup.−4 mbar in the vacuum chamber, molecular oxygen O.sub.2 into the vacuum chamber with an oxygen dose D.sub.o in the range of 0.1 to 1000 Langmuir; whereby a crystalline silicon oxide layer with a thickness of at least two molecular layers is formed within the silicon substrate, between a crystalline silicon base layer and a crystalline silicon top layer. Related semiconductor structures are described.

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

A method for processing a workpiece, a plasma processing apparatus, and a semiconductor device which relate to the field of semiconductor manufacturing are provided. The method includes: placing the workpiece on a workpiece support in a chamber, the workpiece includes an substrate, a portion of the substrate is exposed; performing a flushing process on the workpiece by generating one or more species using a plasma from a process gas to create a mixture, the workpiece is exposed to the mixture; and applying a bias power during the flushing process to form an oxide layer with a preset thickness on the portion of the substrate. In this way, an oxide layer with a preset thickness is obtained after the flushing process.

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.