Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

This disclosure relates to a method (100) for passivating a semiconductor structure, comprising a semiconductor layer and an oxide layer on the semiconductor layer; a semiconductor structure; and a vacuum processing system. The method (100) comprises providing the semiconductor structure (110) in a vacuum chamber (310) and, while keeping the semiconductor structure in the vacuum chamber (120) throughout a refinement period with a duration of at least 25 s refining the oxide layer (130) by maintaining temperature (131) of the semiconductor structure within a refinement temperature range extending from 20° C., to 800° C., and maintaining total pressure (132) in the vacuum chamber below a maximum total pressure, of 1×10.sup.−3 mbar.

A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.

Various embodiments herein relate to methods and apparatus for depositing silicon oxide using thermal ALD or thermal CVD. In one aspect of the disclosed embodiments, a method for depositing silicon oxide is provided, the method including: (a) receiving the substrate in a reaction chamber; (b) introducing a first flow of a first reactant into the reaction chamber and exposing the substrate to the first reactant, where the first reactant includes a silicon-containing reactant; (c) introducing a second flow of a second reactant into the reaction chamber to cause a reaction between the first reactant and the second reactant, (i) where the second reactant includes hydrogen (H2) and an oxygen-containing reactant, (ii) where the reaction deposits silicon oxide on the substrate, and (iii) where the reaction is initiated when a pressure in the reaction chamber is greater than 10 Torr and equal to or less than about 40 Torr.

A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.

A low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation and a preparation method thereof. The low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by the present disclosure includes a substrate layer, a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer, which are arranged in sequence from bottom to top; a cathode arranged on the AlGaN barrier layer; a groove arranged in the GaN channel layer and the AlGaN barrier layer, and an anode provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer; wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal with a crystal orientation of <100>.

Methods are disclosed for forming a Silicon Metal Oxide film using a mono-substituted TSA precursor. The precursors have the formula: (SiH3)2N—SiH2-X, wherein X is selected from a halogen atom; an isocyanato group; an amino group; an N-containing C4-C10 saturated or unsaturated heterocycle; or an alkoxy group.

Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, methods for depositing silicon nitride materials are provided and include heating a workpiece to a temperature of about 200° C. to about 250° C., exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition process, and depositing a nitrogen-rich silicon nitride layer on the workpiece. The deposition gas contains a silicon precursor, a nitrogen precursor, and a carrier gas. A molar ratio of the silicon precursor to the nitrogen precursor to the carrier gas within the deposition gas is about 1:a range from about 4 to about 8:a range from about 20 to about 80, respectively.