An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate; a plurality of bottom electrodes, spaced apart from each other on the substrate; and a protective layer, located in upper portions of the bottom electrodes and separating the bottom electrodes. A material of the protective layer includes hard hydrogenated amorphous carbon.

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a recess between gate spacers of the gate structure by recessing the gate structure below upper surfaces of the gate spacers; depositing a first layer of a dielectric material in the recess along sidewalls and a bottom of the recess; after depositing the first layer, performing a first etching process to remove portions of the first layer of the dielectric material; and after the first etching process, depositing a second layer of the dielectric material in the recess over the first layer of the dielectric material.

A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

A sintered body includes a crystal grain containing silicon nitride, and a grain boundary phase. If dielectric losses of the sintered body are measured while applying an alternating voltage to the sintered body and continuously changing a frequency of the alternating voltage from 50 Hz to 1 MHz, an average value ε.sub.A of dielectric losses of the sintered body in a frequency band from 800 kHz to 1 MHz and an average value ε.sub.B of dielectric losses of the sintered body in a frequency band from 100 Hz to 200 Hz satisfy an expression |ε.sub.A−ε.sub.B|≤0.1.

There is provided a technique that includes selectively doping a metal film with a dopant by performing: supplying a dopant-containing gas containing the dopant to a substrate in which the metal film and a film other than the metal film are formed on a film in which the dopant is doped; and removing the dopant-containing gas from above the substrate.

A semiconductor structure is provided. The semiconductor structure includes a base substrate including a plurality of non-device regions; a middle fin structure and an edge fin disposed around the middle fin structure on the base substrate between adjacent non-device regions; a first barrier layer on sidewalls of the edge fin; and an isolation layer on the base substrate. The isolation layer has a top surface lower than the edge fin and the middle fin structure, and covers a portion of the sidewalls of each of the edge fin and the middle fin structure. The isolation layer further has a material density smaller than the first barrier layer.

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

A method of depositing nitride films is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing nitride films which utilizes separate reaction and nitridation plasmas. In some embodiments, the nitride films have improved growth per cycle (GPC) relative to films deposited by thermal processes or plasma processes with only a single plasma exposure. In some embodiments, the nitride films have improved film quality relative to films deposited by thermal processes or plasma processes with only a single plasma exposure.

A substrate processing method capable of achieving uniform etch selectivity in the entire thickness range of a thin film formed on a stepped structure includes: forming a thin film on a substrate by performing a plurality of cycles including forming at least one layer and applying plasma to the at least one layer under a first process condition; and applying plasma to the thin film under a second process condition different from the first process condition.